View EDJ1108BABG-DG-E_7237585.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

eol produ ct document no. e1248e40 (ver. 4.0) date published april 2009 (k) japan printed in japan url: http://www.elpida.com ? elpida memory, inc. 2007-2009 data sheet 1g bits ddr3 sdram edj1108babg (128m words 8 bits) edj1116babg (64m words 16 bits) specifications ? density: 1g bits organization ? 16m words 8 bits 8 banks (edj1108babg) ? 8m words 16 bits 8 banks (edj1116babg) ? package ? 78-ball fbga (edj1108babg) ? 96-ball fbga (edj1116babg) ? lead-free (rohs compliant) ? power supply: vdd, vddq = 1.5v 0.075v ? data rate ? 1600mbps/1333mbps/1066mbps/800mbps (max.) ? 1kb page size (edj1108babg) ? row address: a0 to a13 ? column address: a0 to a9 ? 2kb page size (edj1116babg) ? row address: a0 to a12 ? column address: a0 to a9 ? eight internal banks for concurrent operation ? interface: sstl_15 ? burst lengths (bl): 8 and 4 with burst chop (bc) ? burst type (bt): ? sequential (8, 4 with bc) ? interleave (8, 4 with bc) ? /cas latency (cl): 5, 6, 7, 8, 9, 10, 11 ? /cas write latency (cwl): 5, 6, 7, 8 ? precharge: auto precharge option for each burst access ? driver strength: rzq/7, rzq/6 (rzq = 240 ? ) ? refresh: auto-refresh, self-refresh ? refresh cycles ? average refresh period 7.8 s at 0 c tc + 85 c 3.9 s at + 85 c < tc + 95 c ? operating case temperature range ? tc = 0 c to +95 c features ? double-data-rate architecture; two data transfers per clock cycle ? the high-speed data transfer is realized by the 8 bits prefetch pipelined architecture ? bi-directional differential data strobe (dqs and /dqs) is transmitted/received with data for capturing data at the receiver ? dqs is edge-aligned with data for reads; center- aligned with data for writes ? differential clock inputs (ck and /ck) ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? data mask (dm) for write data ? posted /cas by programmable additive latency for better command and data bus efficiency ? on-die termination (odt) for better signal quality ? synchronous odt ? dynamic odt ? asynchronous odt ? multi purpose register (mpr) for temperature read out ? zq calibration for dq drive and odt ? programmable partial array self-refresh (pasr) ? /reset pin for power-up sequence and reset function ? srt range: ? normal/extended ? auto/manual self-refresh ? programmable output driver impedance control
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 2 ordering information part number die revision organization (words bits) internal banks jedec speed bin (cl-trcd-trp) package edj1108babg-gl-e edj1108babg-gn-e EDJ1108BABG-DG-E edj1108babg-dj-e edj1108babg-ac-e edj1108babg-ae-e edj1108babg-ag-e edj1108babg-8a-e edj1108babg-8c-e a 128m 8 8 ddr3-1600j (10-10-10) ddr3-1600k (11-11-11) ddr3-1333g (8-8-8) ddr3-1333h (9-9-9) ddr3-1066e (6-6-6) ddr3-1066f (7-7-7) ddr3-1066g (8-8-8) ddr3-800d (5-5-5) ddr3-800e (6-6-6) 78-ball fbga edj1116babg-dg-e edj1116babg-dj-e edj1116babg-ac-e edj1116babg-ae-e edj1116babg-ag-e edj1116babg-8a-e edj1116babg-8c-e 64m 16 ddr3-1333g (8-8-8) ddr3-1333h (9-9-9) ddr3-1066e (6-6-6) ddr3-1066f (7-7-7) ddr3-1066g (8-8-8) ddr3-800d (5-5-5) ddr3-800e (6-6-6) 96-ball fbga part number elpida memory density / bank 11: 1gb / 8-bank organization 08: x8 16: x16 power supply, interface b: 1.5v, sstl_15 die rev. package bg: fbga speed gl: ddr3-1600j (10-10-10) gn: ddr3-1600k (11-11-11) dg: ddr3-1333g (8-8-8) dj: ddr3-1333h (9-9-9) ac: ddr3-1066e (6-6-6) ae: ddr3-1066f (7-7-7) ag: ddr3-1066g (8-8-8) 8a: ddr3-800d (5-5-5) 8c: ddr3-800e (6-6-6) product family j: ddr3 type d: monolithic device e d j 11 08 b a bg - gl - e environment code e: lead free (rohs compliant)
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 3 pin configurations ( 8 configuration) /xxx indicates active low signal. vss vdd 1 vddq vss vss 2 vssq dq0 vss dq2 dq6 vssq vddq vrefdq vss vdd /cs ba0 a7 /reset nc nc vdd 3 nc dqs /dqs dq4 /ras /cas /we ba2 a9 a13 7 nu/(/tdqs) dm/tdqs dq1 vdd dq7 ck /ck a10(ap) nc a11 nc 8 vss vssq vddq vssq dq3 vss dq5 vss vdd zq vrefca a6 a8 cke vss vss 9 vdd vssq vddq nc vdd (top view) 78-ball fbga ( 8 configuration) odt nc a b c d e f g h j a3 vdd a0 a12(/bc) ba1 vdd a5 vss a2 a1 a4 vss k l m n pin name function pin name function a0 to a13* 3 address inputs a10 (ap): auto precharge a12(/bc): burst chop /reset* 3 active low asynchronous reset ba0 to ba2* 3 bank select vdd supply voltage for internal circuit dq0 to dq7 data input/output vss ground for internal circuit dqs, /dqs differential data strobe vddq supply voltage for dq circuit tdqs, /tdqs termination data strobe vssq ground for dq circuit /cs* 3 chip select vrefdq reference voltage for dq /ras, /cas, /we* 3 command input vrefca reference voltage cke* 3 clock enable zq reference pin for zq calibration ck, /ck differential clock input nc* 1 no connection dm write data mask nu* 2 not usable odt* 3 odt control notes: 1. not internally connected with die. 2. don?t connect. internally connected. 3. input only pins (address, command, c ke, odt and /reset) do not supply termination.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 4 pin configurations ( 16 configuration) /xxx indicates active low signal. a b c d e f g h j k l vddq 1 vddq vss nc 2 vdd vss vssq dqu3 vddq vssq vssq vss 3 dqu7 dqu5 dqu1 dmu dql0 vdd /cas /ras 7 dqu4 /dqsu dqsu dqu0 dml /ck 8 vddq dqu6 vssq dqu2 vssq vdd vssq vdd m n p t vss /reset nc nc nc a8 9 vss vddq vddq dql2 dql6 vssq vddq vrefdq dqsl /dqsl dql4 dql1 vdd dql3 vss vssq dql7 dql5 vddq vssq vddq ck vss nc vdd ba0 a3 a5 ba2 a0 a2 a12(/bc) a1 vrefca ba1 a4 vss vss (top view) 96-ball fbga /cs /we odt vss vss r a7 a9 a11 a6 vdd vdd a10(ap) vss vdd nc zq nc cke pin name function pin name function a0 to a12* 2 address inputs a10(ap): auto precharge a12(/bc): burst chop /reset* 2 active low asynchronous reset ba0 to ba2 bank select vdd supply voltage for internal circuit dqu0 to dqu7 dql0 to dql7 data input/output vss ground for internal circuit dqsu, /dqsu dqsl, /dqsl differential data strobe vddq supply voltage for dq circuit /cs* 2 chip select vssq ground for dq circuit /ras, /cas, /we* 2 command input vrefdq reference voltage for dq cke* 2 clock enable vrefca reference voltage ck, /ck differential clock input zq reference pin for zq calibration dmu, dml write data mask nc* no connection odt* 2 odt control note: 1. not internally connected with die. 2. input only pins (address, command, c ke, odt and /reset) do not supply termination.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 5 contents specifications................................................................................................................. ................................1 features....................................................................................................................... ..................................1 ordering in format ion........................................................................................................... ...........................2 part nu mber .................................................................................................................... ..............................2 pin configurations ( 8 configur ation) ............................................................................................................3 pin configurations ( 16 configur ation) ..........................................................................................................4 electrical conditions .......................................................................................................... ............................7 absolute maxi mum ra tings ....................................................................................................... ................... 7 operating temperat ure cond ition ................................................................................................ ................ 7 recommended dc operating conditions (tc = 0 c to +85 c, vdd, vddq = 1.5v 0.075v) ................... 8 ac and dc input measurement levels (tc = 0 c to +85 c, vdd, vddq = 1.5v 0.075v)....................... 8 vref tole rances ................................................................................................................ ......................... 9 input slew ra te dera ting ....................................................................................................... ..................... 10 ac and dc logic input levels for differentia l sign als .......................................................................... ...... 16 single-ended requirements fo r differentia l sign als ............................................................................. ...... 18 ac and dc output measurement levels (tc = 0 c to +85 c, vdd, vddq = 1.5v 0.075v) .................. 21 ac overshoot/undershoo t specific ation.......................................................................................... ........... 23 output driver imped ance........................................................................................................ .................... 24 on-die termination (odt) level s and i-v char acterist ics ........................................................................ .26 odt timing de finiti ons......................................................................................................... ...................... 28 idd measurement conditions (tc = 0 c to +85 c, vdd, vddq = 1.5v 0.075v ) ................................... 32 electrical sp ecifications...................................................................................................... .........................43 dc characteristics 1 (tc = 0 c to +85 c, vdd, vddq = 1.5v 0.075v ) ................................................. 43 dc characteristics 2 (tc = 0 c to +85 c, vdd, vddq = 1.5v 0.075v ) ................................................. 44 pin capacitance (tc = 25 c, vdd, vddq = 1.5v 0.075v ) ..................................................................... 45 standard speed bins ............................................................................................................ ...................... 46 ac characteristics (tc = 0 c to +85 c, vdd, vddq = 1.5v 0.075v, vss, vssq = 0v )....................... 50 block diagram .................................................................................................................. ...........................63 pin function................................................................................................................... ..............................64 command oper ation .............................................................................................................. .....................66 command trut h tabl e ............................................................................................................ .................... 66 cke truth table ................................................................................................................ ......................... 70 simplified stat e diag ram ....................................................................................................... ......................71 reset and initializat ion procedure ............................................................................................. ...............72 power-up and initia lization se quence ........................................................................................... ............. 72 reset and initializati on with stabl e power ..................................................................................... ............. 73 programming the mode register.................................................................................................. ...............74 mode register set command cycle time (tmrd) .................................................................................... .74 mrs command to non-mrs command dela y (tmo d) ............................................................................. 74
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 6 ddr3 sdram mode regi ster 0 [mr0] ............................................................................................... ....... 75 ddr3 sdram mode regi ster 1 [mr1] ............................................................................................... ....... 76 ddr3 sdram mode regi ster 2 [mr2] ............................................................................................... ....... 77 ddr3 sdram mode regi ster 3 [mr3] ............................................................................................... ....... 78 burst length (mr0) ............................................................................................................. ....................... 79 burst type (mr0) ............................................................................................................... ........................ 79 dll enabl e (mr 1) ............................................................................................................... ....................... 80 dll-off mode ................................................................................................................... ........................... 80 dll on/off switch ing proc edure ................................................................................................. ................. 81 additive lat ency (mr1)......................................................................................................... ...................... 83 write level ing (mr 1) ........................................................................................................... ....................... 84 tdqs, /tdqs f unction (mr1) ..................................................................................................... ............... 87 extended temperat ure usag e (mr 2) ............................................................................................... .......... 88 multi purpose r egister (mr3)................................................................................................... .................. 90 operation of t he ddr3 sdram .................................................................................................... ..............98 read timing de finition......................................................................................................... ....................... 98 read oper ation ................................................................................................................. ....................... 102 write timing defini tion........................................................................................................ ...................... 109 write oper ation................................................................................................................ ......................... 110 write timing violat ions ........................................................................................................ ..................... 116 write data mask ................................................................................................................ ....................... 117 prechar ge ...................................................................................................................... ........................... 118 auto precharge operat ion ....................................................................................................... ................. 119 auto-ref resh................................................................................................................... .......................... 120 self-ref resh................................................................................................................... ........................... 121 power-dow n m ode ................................................................................................................ ................... 122 input clock frequency change dur ing precharge power-down............................................................... 129 on-die terminat ion (o dt)....................................................................................................... ................. 130 zq calib ration................................................................................................................. .......................... 142 package drawing ................................................................................................................ ......................144 recommended solder ing conditions............................................................................................... .........146
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 7 electrical conditions ? all voltages are referenced to vss (gnd) ? execute power-up and initialization sequence before proper device oper ation is achieved. absolute maximum ratings parameter symbol rating unit notes power supply voltage vdd ? 0.4 to +1.975 v 1, 3 power supply voltage for output vddq ? 0.4 to +1.975 v 1, 3 input voltage vin ? 0.4 to +1.975 v 1 output voltage vout ? 0.4 to +1.975 v 1 reference voltage vrefca ? 0.4 to 0.6 vdd v 3 reference voltage for dq vrefdq ? 0.4 to 0.6 vddq v 3 storage temperature tstg ? 55 to +100 c 1, 2 power dissipation pd 1.0 w 1 short circuit output current iout 50 ma 1 notes: 1. stresses greater than those listed under abso lute maximum ratings may cause permanent damage to the device. this is a stress rating only and functi onal operation of the devic e at these or any other conditions above those indicated in the operational sectio ns of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface te mperature on the center/t op side of the dram. 3. vdd and vddq must be within 300mv of each other at all times; and vref must be no greater than 0.6 vddq, when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specifi cation. exposure to absolute maximum rating conditions for extended periods may affect device reliability. operating temperature condition parameter symbol rating unit notes operating case temperature tc 0 to +95 c 1, 2, 3 notes: 1. operating tem perature is the case surface temperat ure on the center/top side of the dram. 2. the normal temperature range specifies the temperatur es where all dram specifications will be supported. during operati on, the dram case temperature must be maintained between 0c to +85c under all operating conditions. 3. some applications require operation of the dram in the exte nded temperature range between +85c and +95c case temperature. full s pecifications are guarant eed in this range, but the following additional conditions apply: a) refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9s. (this double refresh requirement may not apply for some devices.) b) if self-refresh operation is required in the extend ed temperature range, t hen it is mandatory to either use the manual self-r efresh mode with extended temperature range capability (mr2 bit [a6, a7] = [0, 1]) or enable the optional auto se lf-refresh mode (mr2 bit [a6, a7] = [1, 0]).
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 8 recommended dc operating conditions (tc = 0 c to +85 c, vdd, vddq = 1.5v 0.075v) parameter symbol min. typ. max. unit notes supply voltage vdd 1.425 1.5 1.575 v 1, 2 supply voltage for dq vddq 1.425 1.5 1.575 v 1, 2 input reference voltage vrefca (dc) 0.49 vdd 0.50 vdd 0.51 vdd v 3, 4 input reference voltage for dq vrefdq (dc) 0.49 vddq 0.50 vddq 0.51 vddq v 3, 4 notes: 1. under all conditions vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd and vddq tied together. 3. the ac peak noise on vref may not allow vref to deviate from vref(dc) by more than 1% vdd (for reference: approx 15 mv). 4. for reference: approx. vdd/2 15 mv. ac and dc input measurement levels (tc = 0 c to +85 c, vdd, vddq = 1.5v 0.075v) single-ended ac and dc input levels for command and address parameter symbol min. typ. max. unit notes dc input logic high vihca (dc) vref + 0.100 ? vdd v 1 dc input logic low vilca (dc) vss ? vref ? 0.100 v 1 ac input logic high vihca (ac) vref + 0.175 ? ? * 2 v 1 ac input logic low vilca (ac) ? * 2 ? vref ? 0.175 v 1 ac input logic high vihca (ac150) vref + 0.150 ? ? * 2 v 1 ac input logic low vilca (ac150) ? * 2 ? vref ? 0.150 v 1 notes: 1. for input only pins except /reset; vref = vrefca. 2. see overshoot and undershoo t specifications section. single-ended ac and dc input levels for dq and dm parameter symbol min. typ. max. unit notes dc input logic high vihdq (dc) vref + 0.100 ? vdd v 1 dc input logic low vildq (dc) vss ? vref ? 0.100 v 1 ac input logic high ddr3-800, 1066 vihdq (ac) vref + 0.175 ? ? * 2 v 1, 3 ddr3-1333, 1600 vihdq (ac) vref + 0.150 ? ? * 2 v 1, 3 ac input logic low ddr3-800, 1066 vildq (ac) ? * 2 ? vref ? 0.175 v 1, 3 ddr3-1333, 1600 vildq (ac) ? * 2 ? vref ? 0.150 v 1, 3 notes: 1. for dq and dm: vref = vrefdq. 2. see overshoot and undershoo t specifications section. 3. single-ended swing requirement for dqs, /dqs is 350 mv (peak to peak). differential swing requirement for dqs, /dqs is 700 mv (peak to peak).
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 9 vref tolerances the dc-tolerance limits and ac-noise limits for the reference voltages vr efca and vrefdq are shown in figure vref(dc) tolerance and vref ac-noise limits. it shows a valid reference voltage vref(t) as a function of time. (vref stands for vrefca and vrefdq likewise). vref(dc) is the linear average of vref(t) over a very long period of time (e.g. 1 sec). this average has to meet the min/max requirements in the tabl e of(single-ended ac and dc input levels for command and address). furthermore vref(t) may temporarily deviate fr om vref(dc) by no more than +/- 1% vdd.

vref(dc) tolerance and vref ac-noise limits the voltage levels for setup and hold time measurement s vih(ac), vih(dc), vil(ac ) and vil(dc) are dependent on vref. vref shall be understood as vref(dc), as defined in fi gure above, vref(dc) tolerance and vref ac-noise limits. this clarifies that dc-variations of vref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. system timing and voltage budgets need to account for vref(dc) deviations from the optimum pos ition within the data-eye of the input signals. this also clarifies that the dram setup/hold specification and derating values need to include time and voltage associated with vref ac-noise. timing and voltage effect s due to ac-noise on vref up to the specified limit ( 1% of vdd) are included in dram timi ngs and their associated deratings.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 10 input slew rate derating for all input signals the total tis, tds (setup time) and tih, t dh (hold time) required is calculated by adding the data sheet tis (base), tds (base) and tih (base), tdh (base) value to the ? tis, ? tds and ? tih, ? tdh derating value respectively. example: tds (total setup time) = tds (base) + ? tds. setup (tis, tds) nominal slew rate for a rising signal is defined as the slew rate betwee n the last crossing of vref (dc) and the first crossing of vih (ac) min. setup (tis, td s) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref (dc) and the firs t crossing of vil (ac) max. if the actual signal is always earlier than the nominal slew rate line between sha ded ?vref (dc) to ac region?, use nominal slew rate for derating value (see the figure of slew rate definition nominal). if the actual signal is later than the nominal slew rate line anywhere between shaded ?vref (dc) to ac region?, the slew rate of a tangent line to the act ual signal from the ac level to dc leve l is used for derating value (see the figure of slew rate definition tangent). hold (tih, tdh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil (dc) max. and the first crossing of vr ef (dc). hold (tih, tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih (dc) min. and the first crossing of vref (dc). if the actual signal is always later than the nominal slew rate line between sh aded ?dc level to vref (dc) region?, use nominal slew rate for derating value (see the figure of slew rate definition nominal). if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to vref (dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref (dc) level is used for derating value (see the figure of slew rate definition tangent). for a valid transition the input signal has to remain above/ below vih/vil(ac) for some ti me tvac (see the table of required time tvac above vih(ac) {below vil(ac)} for valid transition). although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached vih/il (ac) at the time of the rising clock transition) a vali d input signal is still required to complete the transition and reach vih/il (ac). for slew rates in between the values listed in the ta bles below, the derating values may obtained by linear interpolation. these values are typically not subject to production test. they are verified by design and characterization. [address/command setup and hold base-values for 1v/ns] ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit reference tis(base) 200 125 65 45 ps vih/vil(ac) tih(base) 275 200 140 120 ps vih/vil(dc) tis(base) ac150 200 + 150 125 + 150 65 + 125 45 + 125 ps vih/vil(ac) notes: 1 ac/dc referenced for 1v/ns address/command sl ew rate and 2v/ns differential ck, /ck slew rate. 2. the ths (base) ac150 specificati ons are adjusted from the tis(base) s pecification by adding an additional 100ps of derating to accommodate for the lower al ternate threshold of 150mv and another 25ps to account for the earlier reference point [(175mv ? 150mv)/1v/ns]
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 11 [derating values of tis/tih ac/dc based (ddr3-800, 1066, 1333, 1600)] ? tis, ? tih derating in [ps] ac/dc based ac175 threshold -> vih(ac)=vref(dc)+175mv, vil(ac)=vref(dc)-175mv ck, /ck differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih unit 2.0 +88 +50 +88 +50 +88 +50 +96 +58 +104 +66 +112 +74 +120 +84 +128 +100 ps 1.5 +59 +34 +59 +34 +59 +34 +67 +42 +75 +50 +83 +58 +91 +68 +99 +84 ps 1.0 0 0 0 0 0 0 +8 +8 +16 +16 +24 +24 +32 +34 +40 +50 ps 0.9 ? 2 ? 4 ? 2 ? 4 ? 2 ? 4 +6 +4 +14 +12 +22 +20 +30 +30 +38 +46 ps 0.8 ? 6 ? 10 ? 6 ? 10 ? 6 ? 10 +2 ? 2 +10 +6 +18 +14 +26 +24 +34 +40 ps 0.7 ? 11 ? 16 ? 11 ? 16 ? 11 ? 16 ? 3 ? 8 +5 0 +13 +8 +21 +18 +29 +34 ps 0.6 ? 17 ? 26 ? 17 ? 26 ? 17 ? 26 ? 9 ? 18 ? 1 ? 10 +7 ? 2 +15 +8 +23 +24 ps 0.5 ? 35 ? 40 ? 35 ? 40 ? 35 ? 40 ? 27 ? 32 ? 19 ? 24 ? 11 ? 16 ? 2 ? 6 +5 +10 ps cmd, add slew rate (v/ns) 0.4 ? 62 ? 60 ? 62 ? 60 ? 62 ? 60 ? 54 ? 52 ? 46 ? 44 ? 38 ? 36 ? 30 ? 26 ? 22 ? 10 ps [derating values of tis/tih ac/ dc based-alternate ac150 threshold (ddr3-800, 1066, 1333, 1600)] ? tis, ? tih derating in [ps] ac/dc based alternate ac150 threshold -> vih(ac)=vref(dc)+150mv, vil(ac)=vref(dc)-150mv ck, /ck differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih unit 2.0 +75 +50 +75 +50 +75 +50 +83 +58 +91 +66 +99 +74 +107 +84 +115 +100 ps 1.5 +50 +34 +50 +34 +50 +34 +58 +42 +66 +50 +74 +58 +82 +68 +90 +84 ps 1.0 0 0 0 0 0 0 +8 +8 +16 +16 +24 +24 +32 +34 +40 +50 ps 0.9 0 ? 4 0 ? 4 0 ? 4 +8 +4 +16 +12 +24 +20 +32 +30 +40 +46 ps 0.8 0 ? 10 0 ? 10 0 ? 10 +8 ? 2 +16 +6 +24 +14 +32 +24 +40 +40 ps 0.7 0 ? 16 0 ? 16 0 ? 16 +8 ? 8 +16 0 +24 +8 +32 +18 +40 +34 ps 0.6 ? 1 ? 26 ? 1 ? 26 ? 1 ? 26 +7 ? 18 +15 ? 10 +23 ? 2 +31 +8 +39 +24 ps 0.5 ? 10 ? 40 ? 10 ? 40 ? 10 ? 40 ? 2 ? 32 +6 ? 24 +14 ? 16 +22 ? 6 +30 +10 ps cmd, add slew rate (v/ns) 0.4 ? 25 ? 60 ? 25 ? 60 ? 25 ? 60 ? 17 ? 52 ? 9 ? 44 ? 1 ? 36 7 ? 26 15 ? 10 ps [required time tvac above vih(ac) {below vil(ac)} for valid transition] tvac @ 175 mv[ps] tvac @ 150 mv[ps] slew rate (v/ns) min. max. min. max. > 2.0 75 ? 175 ? 2.0 57 ? 170 ? 1.5 50 ? 167 ? 1.0 38 ? 163 ? 0.9 34 ? 162 ? 0.8 29 ? 161 ? 0.7 22 ? 159 ? 0.6 13 ? 155 ? 0.5 0 ? 150 ? < 0.5 0 ? 150 ?
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 12 [data setup and hold base-values] ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit reference tds(base) 75 25 30 10 ps vih/vil(ac) tdh(base) 150 100 65 45 ps vih/vil(dc) notes: 1 ac/dc referenced for 1v/ns dq slew rate and 2v/ns dqs slew rate. [derating values of tds/tdh ac/dc based (ddr3-800, 1066)] ? tds, ? tdh derating in [ps] ac/dc based dqs, /dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh unit 2.0 +88 +50 +88 +50 +88 +50 ? ? ? ? ? ? ? ? ? ? ps 1.5 +59 +34 +59 +34 +59 +34 +67 +42 ? ? ? ? ? ? ? ? ps 1.0 0 0 0 0 0 0 +8 +8 +16 +16 ? ? ? ? ? ? ps 0.9 ? ? ? 2 ? 4 ? 2 ? 4 +6 +4 +14 +12 +22 +20 ? ? ? ? ps 0.8 ? ? ? ? ? 6 ? 10 +2 ? 2 +10 +6 +18 +14 +26 +24 ? ? ps 0.7 ? ? ? ? ? ? ? 3 ? 8 +5 0 +13 +8 +21 +18 +29 +34 ps 0.6 ? ? ? ? ? ? ? ? ? 1 ? 10 +7 ? 2 +15 +8 +23 +24 ps 0.5 ? ? ? ? ? ? ? ? ? ? ? 11 ? 16 ? 2 ? 6 +5 +10 ps dq slew rate (v/ns) 0.4 ? ? ? ? ? ? ? ? ? ? ? ? ? 30 ? 26 ? 22 ? 10 ps [derating values of tds/tdh ac /dc based (ddr3-1333, 1600)] ? tds, ? tdh derating in [ps] ac/dc based dqs, /dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh unit 2.0 +75 +50 +75 +50 +75 +50 ? ? ? ? ? ? ? ? ? ? ps 1.5 +59 +34 +59 +34 +59 +34 +58 +42 ? ? ? ? ? ? ? ? ps 1.0 0 0 0 0 0 0 +8 +8 +16 +16 ? ? ? ? ? ? ps 0.9 ? ? 0 ? 4 0 ? 4 +8 +4 +16 +12 +24 +20 ? ? ? ? ps 0.8 ? ? ? ? ? 10 +8 ? 2 +16 +6 +24 +14 +32 +24 ? ? ps 0.7 ? ? ? ? ? ? +8 ? 8 +16 0 +24 +8 +32 +18 +40 +34 ps 0.6 ? ? ? ? ? ? ? ? +15 ? 10 +23 ? 2 +31 +8 +39 +24 ps 0.5 ? ? ? ? ? ? ? ? ? ? +14 ? 16 +22 ? 6 +30 +10 ps dq slew rate (v/ns) 0.4 ? ? ? ? ? ? ? ? ? ? ? ? +7 ? 26 +15 ? 10 ps
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 13 [required time tvac above vih(ac) {b elow vil(ac)} for valid transition] ddr3-800, 1066 ddr3-1333, 1600 tvac [ps] tvac [ps] slew rate (v/ns) min. max. min. max. > 2.0 75 ? 175 ? 2.0 57 ? 170 ? 1.5 50 ? 167 ? 1.0 38 ? 163 ? 0.9 34 ? 162 ? 0.8 29 ? 161 ? 0.7 22 ? 159 ? 0.6 13 ? 155 ? 0.5 0 ? 150 ? < 0.5 0 ? 150 ?
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 14 vdd tis tih tis tih vref to ac region vref to ac region dc to vref region dc to vref region nominal slew rate nominal slew rate " tfs " trh " tfh " trs vss vih (ac) min. vih (dc) min. vil (dc) max. vil (ac) max. vref (dc) tvac tvac ck /ck slew rate definition nominal (ck, /ck) vdd tds tdh tds tdh /dqs dqs vref to ac region vref to ac region dc to vref region dc to vref region nominal slew rate nominal slew rate " tfs " trh " tfh " trs vss vih (ac) min. vih (dc) min. vil (dc) max. vil (ac) max. vref (dc) tvac tvac slew rate definition nominal (dqs, /dqs) vref (dc) - vil (ac) max. ? tfs setup slew rate falling signal vref (dc) - vil (dc) max. ? trh hold slew rate rising signal = = vih (ac) min. - vref (dc) ? trs setup slew rate rising signal vih (dc) min. - vref (dc) ? tfh hold slew rate falling signal = =
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 15 vdd tis tih tis tih vref (dc) vih (ac) min. vih (dc) min. vil (dc) max. vil (ac) max. vss vref to ac region vref to ac region dc to vref region dc to vref region nominal line nominal line nominal line nominal line tangent line tangent line " tfs " trh " tfh " trs tvac tvac ck /ck slew rate definition tangent (ck, /ck) vdd tds tdh tds tdh vref (dc) vih (ac) min. vih (dc) min. vil (dc) max. vil (ac) max. vss vref to ac region vref to ac region dc to vref region dc to vref region nominal line nominal line nominal line nominal line tangent line tangent line " tfs " trh " tfh " trs /dqs dqs tvac tvac slew rate definition tangent (dqs, /dqs) tangent line [vref (dc) - vil (ac) max.] ? tfs setup slew rate falling signal tangent line [vref (dc) - vil (dc) max.] ? trh hold slew rate rising signal = = tangent line [vih (ac) min. - vref (dc)] ? trs setup slew rate rising signal tangent line [vih (dc) min. - vref (dc)] ? tfh hold slew rate falling signal = =
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 16 ac and dc logic input levels for differential signals differential signal definition

! "#" definition of differential ac-swing and ?time above ac-level? tdvac [differential ac and dc input levels] parameter symbol min. typ. max. unit notes differential input logic high vihdiff + 0.200 ? ? * 3 v 1 differential input logic low vildiff ? * 3 ? ?0.200 v 1 differential input logic ac vihdiff (ac) 2 (vih (ac) ? vref) ? ? * 3 v 2 differential input logic ac vildiff (ac) ? * 3 ? 2 (vref ? vil(ac)) v 2 notes: 1 used to define a differential signal slew-rate. 2. for ck, /ck use vih/vil(ac) of address/comm and and vrefca; for strobes (dqs, /dqs, dqsl, /dqsl, dqsu, /dqsu) use vih/vil( ac) of dqs and vrefdq; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3 these values are not defined, however the single end ed components of differential signal ck, /ck, dqs, /dqs, dqsl, /dqsl, dqsu, /dqsu need to be within th e respective limits (vih(dc) max, vil(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. refer to overshoot and undershoot specifications.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 17 [required time tvac above vih(ac) {b elow vil(ac)} for valid transition] @[vih/ldiff (ac)] = 350 mv @[vih/ldiff (ac)] = 300 mv tdvac [ps] tdvac [ps] slew rate (v/ns) min. max. min. max. > 4.0 75 ? 175 ? 4.0 57 ? 170 ? 3.0 50 ? 167 ? 2.0 38 ? 163 ? 1.8 34 ? 162 ? 1.6 29 ? 161 ? 1.4 22 ? 159 ? 1.2 13 ? 155 ? 1.0 0 ? 150 ? < 1.0 0 ? 150 ?
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 18 single-ended requirements for differential signals each individual component of a differential signal (ck, dqs, dqsl, dqsu, /ck, /dqs, /dqsl or /dqsu) has also to comply with certain requirements for single-ended signals. ck and /ck have to approxim ately reach vseh min. / vsel max. (approximately equal to the ac-levels (vih(ac) / vil(ac)) for address/command signals) in every half-cycle. dqs, dqsl, dqsu, /dqs, /dqsl have to reach vseh min ./vsel max. (approximately the ac-levels (vih(ac) / vil(ac)) for dq signals) in every half-cycle preceding and following a valid transition. note that the applicable ac-levels for address/command and dq?s might be differ ent per speed-bin etc. e.g. if vih 150 (ac)/vil 150 (ac) is used for address/command signals , then these ac-levels apply also for the single ended components of differential ck and /ck.
single-ended requirement for differential signals. note that while address/command and dq signal requir ements are with respect to vref, the single-ended components of differential signals have a requirement with respect to vdd / 2; this is nominally the same. the transition of single-ended signals through the ac-levels is used to measure setup time. for single-ended components of differential signals the requirement to reach vsel max, vseh min has no bearing on timing, but adds a restriction on the common mode characteri stics of these signals.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 19 [single-ended levels for ck, dqs, dqsl , dqsu, /ck, /dqs, /dqsl or /dqsu] parameter symbol min. typ. max. unit notes single-ended high level for strobes (vdd/2) + 0.175 ? ? * 3 v 1, 2 single-ended high level for ck, /ck vseh (vdd/2) + 0.175 ? ? * 3 v 1, 2 single-ended low level for strobes ? * 3 ? (vdd/2) ? 0.175 v 1, 2 single-ended low level for ck, /ck vsel ? * 3 ? (vdd/2) ? 0.175 v 1, 2 notes: 1. for ck, /ck use vih/vil(ac ) of add/cmd; for strobes (dqs, /d qs, dqsl, /dqsl, dqsu, /dqsu) use vih/vil(ac) of dqs. 2. vih(ac)/vil(ac) for dqs is based on vrefd q; vih(ac)/vil(ac) for address/command is based on vrefca; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3 these values are not defined, however the single en ded components of differential signals ck, /ck, dqs, /dqs, dqsl, /dqsl, dqsu, /dqsu need to be within th e respective limits (vih(dc) max, vil(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. refer to overshoot and undershoot specifications. to guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (ck, /ck and dqs, /dqs) must meet the r equirements in table above. the differential input cross point voltage vix is measured fr om the actual cross point of true and complement signal to the midlevel between of vdd and vss. vix vix vix ck, dqs vdd vdd/2 /ck, /dqs vss vix definition [cross point voltage for differential input signals (ck, dqs)] parameter symbol pins min. max. unit note differential input cross point voltage relative to vdd/2 vix ck, /ck ? 150 150 mv ? 175 175 mv 1 vix dqs, /dqs ? 150 150 mv note: 1. extended range for vix is only allowed for cl ock and if ck and /ck are monotonic, have a single-ended swing vsel/vseh of at least vdd/2 +/-250 mv, and the diffe rential slew rate of ck - /ck is larger than 3 v/ ns. refer to the table of cross point voltage for differe ntial input signals (ck, dqs) for vsel and vseh standard values.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 20 [differential input sl ew rate definition] measured description from to defined by applicable for note differential input slew rate for rising edge (ck - /ck and dqs - /dqs) vildiff (max.) vihdiff (min.) vihdiff (min.) ? vildiff (max.) ? trdiff differential input slew rate for falling edge (ck - /ck and dqs - /dqs) vihdiff (min.) vildiff (max.) vihdiff (min.). ? vildiff max. ? tfdiff note: the differential signal (i.e. ck, /ck and dqs, /dqs) must be linear between these thresholds. ? trdiff ? tfdiff vihdiff (min.) ? vildiff (max.) ? tfdiff falling slew = vihdiff(min.) vildiff (max.) 0 vihdiff (min.) ? vildiff (max.) ? trdiff rising slew = differential input slew rate definition for dqs, /dqs and ck, /ck
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 21 ac and dc output measurement levels (tc = 0 c to +85 c, vdd, vddq = 1.5v 0.075v) parameter symbol specification unit notes dc output high measurement level (for iv curve linearity) voh (dc) 0.8 vddq v dc output middle measurement level (for iv curve linearity) vom (dc) 0.5 vddq v dc output low measurement level (for iv curve linearity) vol (dc) 0.2 vddq v ac output high measurement level (for output slew rate) voh (ac) vtt + 0.1 vddq v 1 ac output low measurement level (for output slew rate) vol (ac) vtt ? 0.1 vddq v 1 ac differential output high measurement level (for output slew rate) vohdiff 0.2 vddq v 2 ac differential output low measurement level (for output slew rate) voldiff ? 0.2 vddq v 2 ac differential cross point voltage vox (ac) tbd v notes: 1. the swing of 0.1 vddq is based on approxim ately 50% of the static si ngle-ended output high or low swing with a driver impedance of 34 ? and an effective test load of 25 ? to vtt = vddq/2 at each of the differential outputs. 2. the swing of 0.2 vddq is based on approxim ately 50% of the static si ngle-ended output high or low swing with a driver impedance of 34 ? and an effective test load of 25 ? to vtt = vddq/2 at each of the differential outputs. output slew rate definitions [single-ended output slew rate definition] measured description from to defined by output slew rate for rising edge vol (ac) voh (ac) voh (ac) ? vol (ac) ? trse output slew rate for falling edge voh (ac) vol (ac) voh (ac) ? vol (ac) ? tfse ? trse ? tfse voh (ac) ? vol (ac) ? tfse falling slew = voh (ac) vol (ac) vtt voh (ac) ? vol (ac) ? trse rising slew = input slew rate definition for single-ended signals
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 22 [differential output sl ew rate definition] measured description from to defined by differential output slew rate for rising edge voldiff (ac) vohdiff (ac) vohdiff(ac) ? voldiff (ac) ? trdiff differential output slew rate for falling edge vohdiff (ac) voldiff (ac) vohdiff (ac) ? voldiff (ac) ? tfdiff ? trdiff ? tfdiff vohdiff (ac) ? voldiff (ac) ? tfdiff falling slew = vohdiff (ac) voldiff (ac) 0 vohdiff (ac) ? voldiff (ac) ? trdiff rising slew = differential input slew rate definition for dqs, /dqs and ck, /ck output slew rate (r on = rzq/7 setting) parameter symbol speed min. max. unit notes output slew rate (single-ended) srqse ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 2.5 5 v/ns 1 output slew rate (differential) srqdiff ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 5 12 v/ns 1 remark: sr = slew rate. se = single-ended signals . diff = differential signals. q = query output note: 1. in two cases, a maximum slew rate of 6v/ns appl ies for a single dq signal within a byte lane. (a) is defined for a single dq signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining dq signals in the same byte lane are static (i.e. they stay at either high or low). (b) is defined for a single dq signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining dq signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). for the remaining dq signal switching into the opposite direction, the regul ar maximum limit of 5v/ns applies. reference load for ac timing and output slew rate rt =25 ? = reference output load
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 23 ac overshoot/undershoot specification parameter pins specification maximum peak amplitude allowed for overshoot command, address, cke, odt 0.4v maximum peak amplitude allowed for undershoot 0.4v maximum overshoot area above vdd ddr3-1600 0.33v-ns ddr3-1333 0.4v-ns ddr3-1066 0.5v-ns ddr3-800 0.67v-ns maximum undershoot area below vss ddr3-1600 0.33v-ns ddr3-1333 0.4v-ns ddr3-1066 0.5v-ns ddr3-800 0.67v-ns maximum peak amplitude allowed for overshoot ck, /ck 0.4v maximum peak amplitude allowed for undershoot 0.4v maximum overshoot area above vdd ddr3-1600 0.13v-ns ddr3-1333 0.15v-ns ddr3-1066 0.19v-ns ddr3-800 0.25v-ns maximum undershoot area below vss ddr3-1600 0.13v-ns ddr3-1333 0.15v-ns ddr3-1066 0.19v-ns ddr3-800 0.25v-ns maximum peak amplitude allowed for overshoot dq, dqs, /dqs, dm 0.4v maximum peak amplitude allowed for undershoot 0.4v maximum overshoot area above vddq ddr3-1600 0.13v-ns ddr3-1333 0.15v-ns ddr3-1066 0.19v-ns ddr3-800 0.25v-ns maximum undershoot area below vssq ddr3-1600 0.13v-ns ddr3-1333 0.15v-ns ddr3-1066 0.19v-ns ddr3-800 0.25v-ns maximum amplitude overshoot area undershoot area volts (v) time (ns) vdd, vddq vss, vssq overshoot/undershoot definition
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 24 output driver impedance ron will be achieved by the ddr3 sdram after proper i/o calibration. tolerance and linearity requirements are referred to the output driver dc el ectrical characteristics table. a functional representation of the output buffer is shown in the figure output driver: definition of voltages and currents. ron is defined by the value of the exte rnal reference resistor rzq as follows: ? ron40 = rzq/6 ? ron34 = rzq/7 the individual pull-up and pull-down resistors (ronpu and ronpd) are defined as follows: parameter symbol definition conditions output driver pull-up impedance ronpu vddq ? vout ? iout ? ronpd is turned off output driver pull-down impedance ronpd vout ? iout ? ronpu is turned off vddq vssq v out i out i pu ron pu chip in drive mode to other circuitry like rcv, ... output driver dq i pd ron pd output driver: definition of voltages and currents
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 25 output driver dc electrical characteristics (rzq = 240 ? , entire operating temperature range; after proper zq calibration) ronnom resistor vout min. nom. max. unit notes 40 ? ron40pd vol (dc) = 0.2 vddq vom (dc) = 0.5 vddq voh (dc) = 0.8 vddq 0.6 0.9 0.9 1.0 1.0 1.0 1.1 1.1 1.4 rzq/6 1, 2, 3 ron40pu vol (dc) = 0.2 vddq vom (dc) = 0.5 vddq voh (dc) = 0.8 vddq 0.9 0.9 0.6 1.0 1.0 1.0 1.4 1.1 1.1 rzq/6 1, 2, 3 34 ? ron34pd vol (dc) = 0.2 vddq vom (dc) = 0.5 vddq voh (dc) = 0.8 vddq 0.6 0.9 0.9 1.0 1.0 1.0 1.1 1.1 1.4 rzq/7 1, 2, 3 ron34pu vol (dc) = 0.2 vddq vom (dc) = 0.5 vddq voh (dc) = 0.8 vddq 0.9 0.9 0.6 1.0 1.0 1.0 1.4 1.1 1.1 rzq/7 1, 2, 3 mismatch between pull-up and pull down, mmpupd vom (dc) = 0.5 vddq ? 10 10 % 1, 2, 4 notes: 1. the tolerance limits are specified afte r calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and te mperature sensitivity. 2. the tolerance limits are specified under the condition that vddq = vdd and that vssq = vss. 3. pull-down and pull-up output driver imped ances are recommended to be calibrated at 0.5 vddq. other calibration schemes may be used to achieve the linear ity spec shown above, e. g. calibration at 0.2 vddq and 0.8 vddq. 4. measurement definiti on for mismatch between pull-up and pull-down, mmpupd: measure ronpu and ronpd, both at 0.5 vddq: 100 ronnom ronpd - ronpu mmpupd = output driver temperature and voltage sensitivity if temperature and/or voltage change after calibration, the tole rance limits widen according to the table output driver sensitivity definition and output driver voltage and temperat ure sensitivity. ? t = t ? t (@calibration); ? v= vddq ? vddq (@calibration); vdd = vddq note: drondt and drondv are not subject to production test but are verified by design and characterization. [output driver sensitivity definition] min max unit ronpu@voh (dc) 0.6 ? drondth | ? t| ? drondvh | ? v| 1.1 + drondth | ? t| + drondvh | ? v| rzq/7 ron@ vom (dc) 0.9 ? drondtm | ? t| ? drondvm | ? v| 1.1 + drondtm | ? t| + drondvm | ? v| rzq/7 ronpd@vol (dc) 0.6 ? drondtl | ? t| ? drondvl | ? v| 1.1 + drondtl | ? t| + drondvl | ? v| rzq/7 [output driver voltage and temperature sensitivity] min. max. unit drondtm 0 1.5 %/ c drondvm 0 0.15 %/mv drondtl 0 1.5 %/ c drondvl 0 tbd %/mv drondth 0 1.5 %/ c drondvh 0 tbd %/mv
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 26 on-die termination (odt) levels and i-v characteristics on-die termination effective resistance rtt is defin ed by bits a9, a6 and a2 of the mr1 register. odt is applied to the dq, dm, dqs, /dqs and tdqs, /tdqs ( 8 devices only) pins. a functional representation of the on-die termination is show n in the figure on-die termi nation: definition of voltages and currents. the individual pull-up and pull-down resistors (rttpu and rttpd) are defined as follows: parameter symbol de finition conditions odt pull-up resistance rttpu vddq ? vout ? iout ? rttpd is turned off odt pull-down resistance rttpd vout ? iout ? rttpu is turned off vddq vssq v out i out i pu rtt pu chip in termination mode to other circuitry like rcv, ... odt dq i out = i pd - i pu i pd rtt pd on-die termination: definition of voltages and currents the value of the termination resistor can be set via mr s command to rtt60 = rzq/4 (nom) or rtt120 = rzq/2 (nom). rtt60 or rtt120 will be achieved by the ddr3 sdra m after proper io calibration has been performed. tolerances requirements are referred to t he odt dc electrical characteristics table. measurement definition for rtt apply vih (ac) to pin under test and measure current i(vi h(ac)), then apply vil(ac) to pin under test and measure current i(vil(ac)) respectively. )) ac ( vil ( i )) ac ( vih ( i ) ac ( vil ) ac ( vih rtt ? ? = measurement definition for ? vm measure voltage (vm) at test pin (midpoint) with no load. 100 1 - vddq vm 2 vm ? ? ? ? ? ? ? ? = ?
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 27 odt dc electrical characteristics (rzq = 240 ? , entire operating temperature range; after proper zq calibration) mr1 [a9, a6, a2] rtt resistor vout min. nom. max. unit notes [0, 1, 0] 120 ? rtt120pd240 vol (dc) vom (dc) voh (dc) 0.6 0.9 0.9 1.0 1.0 1.0 1.1 1.1 1.4 rzq 1, 2, 3, 4 rtt120pu240 vol (dc) vom (dc) voh (dc) 0.9 0.9 0.6 1.0 1.0 1.0 1.4 1.1 1.1 rzq 1, 2, 3, 4 rtt120 vil (ac) to vih (ac) 0.9 1.0 1.6 rzq/2 1, 2, 5 [0, 0, 1] 60 ? rtt60pd120 vol (dc) vom (dc) voh (dc) 0.6 0.9 0.9 1.0 1.0 1.0 1.1 1.1 1.4 rzq/2 1, 2, 3, 4 rtt60pu120 vol (dc) vom (dc) voh (dc) 0.9 0.9 0.6 1.0 1.0 1.0 1.4 1.1 1.1 rzq/2 1, 2, 3, 4 rtt60 vil (ac) to vih (ac) 0.9 1.0 1.6 rzq/4 1, 2, 5 [0, 1.1] 40 ? rtt40pd80 vol (dc) vom (dc) voh (dc) 0.6 0.9 0.9 1.0 1.0 1.0 1.1 1.1 1.4 rzq/3 1, 2, 3, 4 rtt40pu80 vol (dc) vom (dc) voh (dc) 0.9 0.9 0.6 1.0 1.0 1.0 1.4 1.1 1.1 rzq/3 1, 2, 3, 4 rtt40 vil (ac) to vih (ac) 0.9 1.0 1.6 rzq/6 1, 2, 5 [1, 0, 1] 30 ? rtt30pd60 vol (dc) vom (dc) voh (dc) 0.6 0.9 0.9 1.0 1.0 1.0 1.1 1.1 1.4 rzq/4 1, 2, 3, 4 rtt30pu60 vol (dc) vom (dc) voh (dc) 0.9 0.9 0.6 1.0 1.0 1.0 1.4 1.1 1.1 rzq/4 1, 2, 3, 4 rtt30 vil (ac) to vih (ac) 0.9 1.0 1.6 rzq/8 1, 2, 5 [1, 0, 0] 20 ? rtt20pd40 vol (dc) vom (dc) voh (dc) 0.6 0.9 0.9 1.0 1.0 1.0 1.1 1.1 1.4 rzq/6 1, 2, 3, 4 rtt20pu40 vol (dc) vom (dc) voh (dc) 0.9 0.9 0.6 1.0 1.0 1.0 1.4 1.1 1.1 rzq/6 1, 2, 3, 4 rtt20 vil (ac) to vih (ac) 0.9 1.0 1.6 rzq/12 1, 2, 5 deviation of vm w.r.t. vddq/2, ? vm ? 5 5 % 1, 2, 5, 6 notes: 1. the tolerance limits are specified afte r calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and te mperature sensitivity. 2. the tolerance limits are specified under the condition that vddq = vdd and that vssq = vss. 3. pull-down and pull-up output resistor s are recommended to be calibrated at 0.5 vddq. other calibration schemes may be used to achieve the linearity spec sh own above, e.g. calibration at 0.2 vddq and 0.8 vddq. 4. not a specification requ irement, but a design guide line. 5. measurement definition for rtt: apply vih (ac) to pin under test and measure curr ent i(vih(ac)), then apply vi l(ac) to pin under test and measure current i(vil(ac)) respectively. )) ac ( vil ( i )) ac ( vih ( i ) ac ( vil ) ac ( vih rtt ? ? =
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 28 6. measurement definition for vm and ? vm: measure voltage (vm) at test pin (midpoint) with no load: 100 1 - vddq vm 2 vm ? ? ? ? ? ? ? ? = ? odt temperature and voltage sensitivity if temperature and/or voltage change after calibration, t he tolerance limits widen according to the table odt sensitivity definition and odt volt age and temperature sensitivity. ? t = t ? t (@calibration); ? v= vddq ? vddq (@calibration); vdd = vddq note: drttdt and drttdv are not subject to production test but are verified by design and characterization. [odt sensitivity definition] min. max. unit rtt 0.9 ? drttdt | ! t| - drttdv | ! v| 1.6 + drttdt | ! t| + drttdv | ! v| rzq/2, 4, 6, 8, 12 [odt voltage and temperature sensitivity] min. max. unit drttdt 0 1.5 %/ c drttdv 0 0.15 %/mv odt timing definitions test load for odt timings different than for timing measurements, the reference load for odt timings are defined in odt timing reference load. rt =25 $ vddq ck, /ck vtt = vssq/2 dut dq dqs, /dqs odt timing reference load
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 29 odt measurement definitions definitions for taon, taonpd, taof, taofpd and tadc are provided in the following table and subsequent figures. symbol begin point definiti on end point definition figure taon rising edge of ck - /ck defined by the end point of odtlon extrapolated point at vssq figure a) taonpd rising edge of ck - /ck with odt being first registered high extrapolated point at vssq figure b) taof rising edge of ck - /ck defined by the end point of odtloff end point: extrapolated point at vrtt_nom figure c) taofpd rising edge of ck - /ck with odt being first registered low end point: extrapolated point at vrtt_nom figure d) tadc rising edge of ck - /ck defined by the end point of odtlcnw, odtlcwn4 or odtlcwn8 end point: extrapolated point at vrtt_wr and vrtt_nom respectively figure e) reference settings for odt timing measurements measurement reference settings are pr ovided in the following table. measured parameter rtt_nom setting rtt_wr setting vsw1 [v] vsw2 [v] note taon rzq/4 n/a 0.05 0.10 rzq/12 n/a 0.10 0.20 taonpd rzq/4 n/a 0.05 0.10 rzq/12 n/a 0.10 0.20 taof rzq/4 n/a 0.05 0.10 rzq/12 n/a 0.10 0.20 taofpd rzq/4 n/a 0.05 0.10 rzq/12 n/a 0.10 0.20 tadc rzq/12 rzq/2 0.20 0.30 ck begin point: rising edge of ck - /ck defined by the end point of odtlon end point: extrapolated point at vssq taon tsw2 vsw2 vsw1 tsw1 /ck vssq dq, dm dqs, /dqs tdqs, /tdqs vtt vssq a) definition of taon
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 30 ck begin point: rising edge of ck - /ck with odt being first registered high end point: extrapolated point at vssq taonpd tsw2 vsw2 vsw1 tsw1 /ck vssq dq, dm dqs, /dqs tdqs, /tdqs vtt vssq b) definition of taonpd ck begin point: rising edge of ck - /ck defined by the end point of odtloff end point: extrapolated point at vrtt_nom vrtt_nom taof tsw2 vsw2 vsw1 tsw1 /ck dq, dm dqs, /dqs tdqs, /tdqs vtt vssq c) definition of taof begin point: rising edge of ck - /ck with odt being first registered low ck end point: extrapolated point at vrtt_nom vrtt_nom taofpd tsw2 vsw2 vsw1 tsw1 /ck dq, dm dqs, /dqs tdqs, /tdqs vtt vssq d) definition of taofpd
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 31 ck begin point: rising edge of ck - /ck defined by the end point of odtlcnw begin point: rising edge of ck - /ck defined by the end point of odtlcwn4 or odtlcwn8 end point: extrapolated point at vrtt_wr tadc tsw21 tsw11 vsw2 tsw12 tsw22 vsw1 /ck tadc vrtt_wr vrtt_nom vrtt_nom dq, dm dqs, /dqs tdqs, /tdqs end point: extrapolated point at vrtt_nom vtt vssq e) definition of tadc
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 32 idd measurement conditions (tc = 0 c to +85 c, vdd, vddq = 1.5v 0.075v) within the tables about idd measurement conditions, the fo llowing definitions are used: ? l: vin vil (ac)(max.) ? h: vin vih (ac)(min.); ? stable: inputs are stable at h or l level ? floating: inputs are vref = vddq / 2 ? switching: described in the following definition of switching table. ? n/a: not available [definition of switching] signals definitions address (row, column) if not otherwise mentioned the inputs are stable at h or l during 4 clocks and change then to the opposite value (e.g. ax ax ax ax /ax /ax /ax /ax ax ax ax ax ..... please see each iddx de finition for details bank address if not otherwise mentioned the bank addresses should be switched like the row/column addresses - please see each iddx definition for details command (/cs, /ras, /cas, /we) define d = {/cs, /ras, /cas, /we } := {h, l, l, l} define /d = {/cs, /ras, /cas, /we } := {h, h, h, h} define command background pattern = d d /d /d d d /d /d d d /d /d ... if other commands are necessary (e.g. act for idd0 or read for idd4r) the background pattern command is substituted by the respective /cs, /ras, /cas, /we levels of the necessary command. see each iddx definition for det ails and figures of example of idd1, idd2n/idd3n, idd4r. data (dq) data dq is changing between h and l every other dat a transfer (once per clock) for dq signals, which means that data dq is stable during one clock; see each iddx definition for exceptions from this rule and for further details. see figures of example of idd1, idd2n/idd3n, idd4r. data masking (dm) no switching; dm must be driven l all the time ac timing for idd test conditions for purposes of idd testing, the foll owing parameters are to be utilized. ddr3-1600 ddr3-1333 ddr3-1066 ddr3-800 parameter 10-10-10 11-11-11 8-8-8 9-9-9 6-6-6 7-7-7 8-8-8 5-5-5 6-6-6 unit cl (idd) 10 11 8 9 6 7 8 5 6 tck tck min.(idd) 1.25 1.25 1.5 1.5 1.875 1.875 1.875 2.5 2.5 ns trcd min. (idd) 12.5 13.75 12 13.5 11.25 13.13 15 12.5 15 ns trc min. (idd) 47.5 48.75 48 49.5 48.75 50.63 52.50 50 52.5 ns tras min.(idd) 35 35 36 36 37.5 37.5 37.5 37.5 37.5 ns trp min. (idd) 12.5 13.75 12 13.5 11.25 13.13 15 12.5 15 ns tfaw (idd)- 8 30 30 30 30 37.5 37.5 37.5 40 40 ns tfaw (idd)- 16 ? ? 45 45 50 50 50 50 50 ns trrd (idd)- 8 6.0 6.0 6.0 6.0 7.5 7.5 7.5 10 10 ns trrd (idd)- 16 ? ? 7.5 7.5 10 10 10 10 10 ns trfc (idd) 110 110 110 110 110 110 110 110 110 ns
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 33 the following conditions apply: ? idd specifications are tested after the device is properly initialized. ? input slew rate is specified by ac parametric test conditions. ? idd parameters are specified with odt and output buffer disabled (mr1 bit a12 = 1). idd measurement condition s for idd0 and idd1 symbol idd0 idd1 name operating current 0 -> one bank activate -> precharge operating current 1 -> one bank activate -> read -> precharge measurement condition timing diagram example ? figure idd1 example cke h h external clock on on tck tck min (idd) tck min (idd) trc trc min (idd) trc min (idd) tras tras min (idd) tras min (idd) trcd n/a trcd min (idd) trrd n/a n/a cl n/a cl(idd) al n/a 0 /cs h between. activate and precharge comm ands h between activate, read and precharge command inputs (/cs, /ras, /cas, /we) switching (see definition of switching table); only exceptions are activate and precharge commands; example of idd0 pattern: a0 d /d /d d d /d /d d d /d/d d d /d p0 (ddr3-800: tras = 37.5ns between (a)ctivate and (p)recharge to bank 0; definition of d and /d : see definition of switching table switching (see definition of switching table); only exceptions are activate, read and precharge commands; example of idd1 pattern: a0 d /d /d d r0 /d /d d d /d/d d d /d p0 (ddr3-800 -555: trcd = 12.5ns between (a)ctivate and (r)ead to bank 0; definition of d and /d : see definition of switching table row, column addresses row addresses switching (see definition of switching table); a10 must be l all the time! row addresses switching (see definition of switching table);a10 must be l all the time! bank addresses bank address is fixed (bank 0) bank address is fixed (bank 0) data i/o switching (see definition of switching table) read data: output data switches every clock, which means that read data is stable during one clock cycle. to achieve iout = 0ma the output buffer should be switched off by mr1 bit a12 set to ?1?. when there is no read data burst from dram the dq i/o should be floating. output buffer dq, dqs / mr1 bit a12 off / 1 off / 1 odt / mr1 bits [a9, a6, a2] / mr2 bits [a1, a0] disabled / [0,0,0] / [0,0] disabled / [0,0,0] / [0,0] burst length n/a 8 fixed / mr0 bits [a1, a0] = {0,0} active banks one act-pre loop one act-read-pre loop idle banks all other all other precharge power-down mode / mr0 bit a12 n/a n/a
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 34 3ff /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 t14 t15 t16 t17 t18 address (a0 to a9) address (a10) dq dm 000 00110011 command 000 3ff 000 11 address (a11 to a12) 00 00 00 00 0 ba 0 to 2 /cs /ras /cas /we 11 l act d /d /d d read /d /d /d /d dd /d /d dd /d pre d d idd1 measurement loop 3ff idd1 example* (ddr3-800-555, 512mb 8) note: data dq is shown but the output buffer should be switched off (per mr1 bit a12 = 1) to achieve iout = 0ma. address inputs are split into 3 parts.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 35 idd measurement condition s for idd2n, idd2p (1), idd2p (0) and idd2q symbol idd2n idd2p (1)* 1 idd2p (0)* 1 idd2q name precharge standby current precharge power-down current (fast exit mr0 bit a12= 1) precharge power-down current (slow exit mr0 bit a12= 0) precharge quiet standby current measurement condition timing diagram example figure idd2n/idd3n example ? ? ? cke h l l h external clock on on on on tck tck min (idd) tck min (idd) tck min (idd) tck min (idd) trc n/a n/a n/a n/a tras n/a n/a n/a n/a trcd n/a n/a n/a n/a trrd n/a n/a n/a n/a cl n/a n/a n/a n/a al n/a n/a n/a n/a /cs h stable stable h bank address, row address and command inputs switching (see definition of switching table) stable stable stable data inputs switching floating floating floating output buffer dq, dqs / mr1 bit a12 off / 1 off / 1 off / 1 off / 1 odt / mr1 bits [a9, a6, a2] / mr2 bits [a1, a0] disabled / [0,0,0] / [0,0] disabled / [0,0,0] / [0,0] disabled / [0,0,0] / [0,0] disabled / [0,0,0] / [0,0] burst length n/a n/a n/a n/a active banks none none none none idle banks all all all all precharge power-down mode / mr0 bit a12 n/a fast exit / 1 (any valid command after txp* 2 ) slow exit / 0 slow exit (read and odt commands must satisfy txpdll-al) n/a notes: 1. in ddr3 the mr0 bit a12 defines dll-on/off behaviors only for precharge power-down. there are two different precharge power-down states possible: one wi th dll-on (fast exit, bit a12 = 1) and one with dll-off (slow exit, bit a12 = 0). 2. because it is an exit after precharge power-down the valid commands are: bank activate (act), auto- refresh (ref), mode register set (mrs), self-refresh (self).
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 36 1fff /ck ck t0 t2 t4 t6 t8 t1 t3 t5 t7 t9 address (a0 to a12) dq 0 to 7 dm 0000 command 0000 7 0 0 ba 0 to 2 /cs /ras /cas /we h idd2n/ idd3n measurement loop /d /d d d /d /d d d d /d /d 00 ff ff 00 00 ff 00 00 00 ff ff 00 00 ff ff 00 ff 00 00 ff ff 00 ff idd2n/idd3n example (ddr3-800-555, 512mb 8)
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 37 idd measurement conditions fo r idd3n, idd3p (fast exit) symbol idd3n idd3p (1) name active standby current active power-down current* (always fast exit) measurement condition timing diagram example fi gure idd2n/idd3n example ? cke h l external clock on on tck tck min (idd) tck min (idd) trc n/a n/a tras n/a n/a trcd n/a n/a trrd n/a n/a cl n/a n/a al n/a n/a /cs h stable address and command inputs switchin (see definition of switching table) stable data inputs switching (see definition of switching table) floating output buffer dq, dqs / mr1 bit a12 off / 1 off / 1 odt / mr1 bits [a9, a6, a2] / mr2 bits [a1, a0] disabled / [0,0,0] / [0,0] disabled / [0,0,0] / [0,0] burst length n/a n/a active banks all all idle banks none none precharge power-down mode / mr0 bit a12 n/a n/a (active power-down mode is always ?fast exit? with dll-on) note: ddr3 will offer only one active power-down mode with dll-on (-> fast exit). mr0 bit a12 will not be used for active power-down. instead bit a12 will be used to switch between two different precharge power-down modes.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 38 idd measurement conditions fo r idd4r, idd4w and idd7 symbol idd4r idd4w idd7 name operating current (burst read operating) operating current (burst write operating) all bank interleave read current measurement condition timing diagram example idd4r example ? ? cke h h h external clock on on on tck tck min (idd) tck min (idd) tck min (idd) trc n/a n/a trc min. (idd) tras n/a n/a tras min. (idd) trcd n/a n/a trcd min. (idd) trrd n/a n/a trrd min. (idd) cl cl (idd) cl (idd) cl (idd) al 0 0 trcd min. ? 1tck /cs h between valid commands h between valid commands h between valid commands command inputs (/cs, /ras, /cas, /we) switching (see definition of switching table); only exceptions are read commands -> idd4r pattern: r0 d /d /d r1 d /d /d r2 d /d /d r3 d /d /d r4 ..... rx = read from bank x; definition of d and /d: see definition of switching table switching (see definition of switching table); only exceptions are write commands -> idd4w pattern: w0 d /d /d w1 d /d /d w2 d /d /d w3 d /d /d w4... wx = write to bank x; definition of d and /d: see definition of switching table for patterns see pattern in idd7 timing patterns section row, column addresses column addresses switching (see definition of switching table); a10 must be l all the time! column addresses switching (see definition of switching table); a10 must be l all the time! stable during deselects bank addresses bank address cycling (0 -> 1 -> 2 -> 3 ...) bank address cycling (0 -> 1 -> 2 -> 3 ...) bank address cycling (0 -> 1 -> 2 -> 3 ...), see pattern in idd7 timing patterns section data i/o seamless read data burst (bl8): output data switches every clock, which means that read data is stable during one clock cycle. to achieve iout = 0ma the output buffer should be switched off by mr1 bit a12 set to ?1?. seamless write data burst (bl8): input data switches every clock, which means that write data is stable during one clock cycle. dm is low all the time read data (bl8): output data switches every clock, which means that read data is stable during one clock cycle. to achieve iout = 0ma the output buffer should be switched off by mr1 bit a12 set to ?1?. output buffer dq, dqs / mr1 bit a12 off / 1 off / 1 off / 1 odt / mr1 bits [a9, a6, a2] / mr2 bits [a1, a0] disabled / [0,0,0] / [0,0] disabled / [0,0,0] / [0,0] disabled / [0,0,0] / [0,0] burst length 8 fixed / mr0 [a1, a0] = {0,0} 8 fixed / mr0 bits [a1, a0] = {0,0} 8 fixed / mr0 bits [a1, a0] = {0,0} active banks all all all, rotational idle banks none none none precharge power-down mode / mr0 bit a12 n/a n/a n/a
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 39 3ff /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 address (a0 to a9) address (a10) dq 0 to 7 dm 000 command 0 to 2 000 11 address (a11 to a12) 00 00 11 ba 0 to 2 /cs /ras /cas /we l d read d /d /d read d/d/d /d/d read d read start of measurement loop 3ff 1 0 2 3 00 ff ff 00 ff ff 00 00 ff ff 00 00 00 ff ff 00 idd4r example* (ddr3-800-555, 512mb 8) note: data dq is shown but the output buffer should be switched off (per mr1 bit a12 = 1) to achieve iout = 0ma. address inputs are split into 3 parts.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 40 idd7 timing patterns the detailed timings are shown in the idd7 timing patterns for 8 banks tables. speed bins bin organization tfaw (ns) tfaw (tck) trrd (ns) trrd (tck) timing patterns ddr3-800 all 8 40 16 10 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d all 16 50 20 10 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d d d ddr3-1066 all 8 37.5 20 7.5 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d d d all 16 50 27 10 6 a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d d d d a3 ra3 d d d d d d d a4 ra4 d d d d a5 ra5 d d d d a6 ra6 d d d d a7 ra7 d d d d d d d ddr3-1333 all 8 30 20 6 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d d d all 16 45 30 7.5 5 a0 ra0 d d d a1 ra1 d d d a2 ra2 d d d a3 ra3 d d d d d d d d d d d d d a4 ra4 d d d a5 ra5 d d d a6 ra6 d d d a7 ra7 d d d d d d d d d d d d d ddr3-1600 all 8 30 24 6 5 a0 ra0 d d d a1 ra1 d d d a2 ra2 d d d a3 ra3 d d d d d d d a4 ra4 d d d a5 ra5 d d d a6 ra6 d d d a7 ra7 d d d d d d d remark: ax = active command for bank x. rax = read with auto precharge command from bank x. ex. ra0 = reada command from bank 0 notes: 1. all banks are being interleaved at minimum trc (idd) without violating trrd (idd) and tfaw (idd) using a burst length = 8. 2. control and address bus inputs are stable during deselects. 3. iout = 0ma.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 41 idd measurement c onditions for idd5b symbol idd5b name burst refresh current measurement condition timing diagram example cke h external clock on tck tck min. (idd) trc n/a tras n/a trcd n/a trrd n/a trfc trfc min. (idd) cl n/a al n/a /cs h between valid commands address and command inputs switching data inputs switching output buffer dq, dqs / mr1 bit a12 off / 1 odt / mr1 bits [a9, a6, a2] / mr2 bits [a1, a0] disabled / [0,0,0] / [0,0] burst length n/a active banks refresh command every trfc = trfc (min.) idle banks none precharge power-down mode / mr0 bit a12 n/a
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 42 idd measurement condition s for idd6 and idd6et symbol idd6 idd6et name self-refresh current normal temperature range tc = 0 to +85 c self-refresh current extended temperature range tc = 0 to +95 c measurement condition temperature tc = +85 c tc = +95 c auto self-refresh (asr) / mr2 bit a6 disabled / 0 disabled / 0 self-refresh temperature range (srt) / mr2 bit a7 disabled / 0 enabled / 1 cke l l external clock off; ck and /ck at l off; ck and /ck at l tck n/a n/a trc n/a n/a tras n/a n/a trcd n/a n/a trrd n/a n/a cl n/a n/a al n/a n/a /cs floating floating command inputs /ras, /cas, /we) floating floating row, column addresses floating floating bank addresses floating floating data i/o floating floating output buffer dq, dqs / mr1 bit a12 off / 1 off / 1 odt / mr1 bits [a9, a6, a2] / mr2 bits [a1, a0] disabled / [0,0,0] / [0,0] disabled / [0,0,0] / [0,0] burst length 8 fixed / mr0 bits [a1, a0] = {0,0} 8 fixed / mr0 bits [a1, a0] = {0,0} active banks all during self-refresh ac tions all during self-refresh actions idle banks all between self-refresh actions all between self-refresh actions precharge power-down mode / mr0 bit a12 n/a n/a idd6 current definition parameter symbol parameter/condition normal temperature range self- refresh current idd6 cke 0.2v; external clock off, ck and /ck at 0v; other control and address inputs are floating; data bus inputs are floating, pasr disabled. applicable for mr2 settings a6 = 0 and a7 = 0. extended temperature range self-refresh current idd6et cke 0.2v; external clock off, ck and /ck at 0v; other control and address inputs are floating; data bus inputs are floating, pasr disabled. applicable for mr2 settings a6 = 0 and a7 = 1 auto self-refresh current idd6tc cke 0.2v; external clock off, ck and /ck at 0v; other control and address inputs are floating; data bus inputs are floating, pasr disabled. applicable when asr is enabled by mr2 settings a6 = 1 and a7 = 0.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 43 electrical specifications dc characteristics 1 (tc = 0 c to +85 c, vdd, vddq = 1.5v 0.075v) 8 16 parameter symbol data rate (mbps) max. max. unit notes operating current (act-pre) idd0 1600 1333 1066 800 tbd 120 110 100 ? 140 130 115 ma operating current (act-read-pre) idd1 1600 1333 1066 800 tbd 140 125 115 ? 170 155 140 ma idd2pf 1600 1333 1066 800 tbd 40 35 30 ? 40 35 30 ma fast pd exit precharge power-down standby current idd2ps 1600 1333 1066 800 tbd 14 13 12 ? 14 13 12 ma slow pd exit precharge quiet standby current idd2q 1600 1333 1066 800 tbd 70 60 50 ? 70 60 50 ma precharge standby current idd2n 1600 1333 1066 800 tbd 75 65 55 ? 75 65 55 ma active power-down current (always fast exit) idd3p 1600 1333 1066 800 tbd 45 40 35 ? 45 40 35 ma active standby current idd3n 1600 1333 1066 800 tbd 85 75 65 ? 95 85 75 ma operating current (burst read operating) idd4r 1600 1333 1066 800 tbd 220 180 140 ? 290 230 180 ma operating current (burst write operating) idd4w 1600 1333 1066 800 tbd 240 200 160 ? 330 270 220 ma burst refresh current idd5b 1600 1333 1066 800 tbd 335 315 295 ? 335 315 295 ma all bank interleave read current idd7r 1600 1333 1066 800 tbd 345 285 260 ? 380 330 315 ma
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 44 self-refresh current (tc = 0 c to +85 c, vdd, vddq = 1.5v 0.075v) 8 16 parameter symbol grade max. max. unit notes self-refresh current normal temperature range idd6s 10 10 ma self-refresh current extended temperature range idd6et 18 18 ma auto self-refresh current idd6tc 18 18 ma dc characteristics 2 (tc = 0 c to +85 c, vdd, vddq = 1.5v 0.075v) parameter symbol value unit notes input leakage current ? ili ? 2 a vdd vin vss output leakage current ? ilo ? 5 a vddq vout vss
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 45 pin capacitance (tc = 25 c, vdd, vddq = 1.5v 0.075v) parameter symbol pins min. max. unit notes input pin capacitance, ck and /ck ddr3-1600, 1333 0.8 1.4 pf 1, 3 ddr3-1066, 800 cck 0.8 1.6 pf 1, 3 delta input pin capacitance, ck and /ck ddr3-1600, 1333 0 0.15 pf 1, 2 ddr3-1066, 800 cdck ck, /ck 0 0.15 pf 1, 2 input pin capacitance, control pins ddr3-1600, 1333 0.75 1.3 pf 1 ddr3-1066, 800 cin_ctrl /cs, cke, odt 0.75 1.5 pf 1 input pin capacitance, address and command pins ddr3-1600, 1333 0.75 1.3 pf 1 ddr3-1066, 800 cin_add_cmd /ras, /cas, /we, address 0.75 1.5 pf 1 delta input pin capacitance, control pins ddr3-1600, 1333 ? 0.4 0.2 pf 1, 4 ddr3-1066, 800 cdin_ctrl /cs, cke, odt ? 0.5 0.3 pf 1, 4 delta input pin capacitance, address and command pins ddr3-1600, 1333 ? 0.4 0.4 pf 1, 5 ddr3-1066, 800 cdin_add_cmd /ras, /cas, /we, address ? 0.5 0.5 pf 1, 5 input/output pin capacitance ddr3-1600 1.5 2.3 pf 1, 6 ddr3-1333 1.5 2.5 pf 1, 6 ddr3-1066, 800 cio 1.5 3.0 pf 1, 6 delta input/output pin capacitance ddr3-1600, 1333 ? 0.5 0.3 pf 1, 7, 8 ddr3-1066, 800 cdio dq, dqs, /dqs, tdqs, /tdqs dm ? 0.5 0.3 pf 1, 7, 8 delta input/output pin capacitance ddr3-1600, 1333 0 0.15 pf 1, 10 ddr3-1066, 800 cddqs dqs, /dqs 0 0.2 pf 1, 10 input/output pin capacitance of zq czq zq ? 3 pf 1, 9 notes: 1. vdd, vddq, vss, vssq applied and all ot her pins (except the pin under test) floating. vdd = vddq =1.5v, vbias=vdd/2 2. absolute value of cck(ck-pin) ? cck(/ck-pin) 3. cck (min.) will be equal to cin (min.) 4. cdin_ctrl = cin_ctrl ? 0.5 (cck(ck-pin) + cck(/ck-pin)) 5. cdin_add_cmd = cin_add_cmd ? 0.5 (cck(ck-pin) + cck(/ck-pin)) 6. although the dm, tdqs and /tdqs pins have diffe rent functions, the loading matches dq and dqs. 7. dq should be in hi gh impedance state. 8. cdio = cio (dq, dm) ? 0.5 (cio(dqs-pin) + cio(/dqs-pin)). 9. maximum external load capacitance on zq pin : 5pf. 10 absolute va lue of cio(dqs) ? cio(/dqs)
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 46 standard speed bins [ddr3-1600 speed bins] speed bin ddr3-1600 ddr3-1600 cl-trcd-trp 10-10-10 11-11-11 symbol /cas write latency min. max. min. max. unit notes taa 12.5 20 13.75 20 ns trcd 12.5 ? 13.75 ? ns trp 12.5 ? 13.75 ? ns trc 47.5 ? 48.75 ? ns tras 35 9 trefi 35 9 trefi ns 9 tck (avg)@cl=5 cwl = 5 2.5 3.3 reserved reserved ns 1, 2, 3, 4, 8 cwl = 6, 7, 8 reserved reserved reserved reserved ns 4 tck (avg)@cl=6 cwl = 5 2.5 3.3 2.5 3.3 ns 1, 2, 3, 8 cwl = 6 reserved reserved reserved reserved ns 1, 2, 3, 4, 8 cwl = 7, 8 reserved reserved reserved reserved ns 4 tck (avg)@cl=7 cwl = 5 reserved reserved reserved reserved ns 4 cwl = 6 1.875 < 2.5 reserved reserved ns 1, 2, 3, 4, 8 cwl = 7 reserved reserved reserved reserved ns 1, 2, 3, 4 cwl = 8 reserved reserved reserved reserved ns 1, 2, 3, 4 tck (avg)@cl=8 cwl = 5 reserved reserved reserved reserved ns 4 cwl = 6 1.875 < 2.5 1.875 < 2.5 ns 1, 2, 3, 8 cwl = 7 reserved reserved reserved reserved ns 1, 2, 3, 4 cwl = 8 reserved reserved reserved reserved ns 1, 2, 3, 4 tck (avg)@cl=9 cwl = 5, 6 reserved reserved reserved reserved ns 4 cwl= 7 1.5 < 1.875 reserved reserved ns 1, 2, 3, 4 cwl= 8 reserved reserved reserved reserved ns 1, 2, 3, 4 tck (avg)@cl=10 cwl = 5, 6 reserved reserved reserved reserved ns 4 cwl= 7 1.5 < 1.875 1.5 < 1.875 ns 1, 2, 3 cwl= 8 1.25 < 1.5 reserved reserved ns 5 tck (avg)@cl=11 cwl = 5, 6, 7 reserved reserved reserved reserved ns 4 cwl= 8 1.25 < 1.5 1.25 < 1.5 ns 1, 2, 3 cwl= 8 optional optional 1.25 < 1.5 5 supported cl settings 5, 6, 7, 8, 9, 10 6, 8, 10, 11 nck supported cwl settings 5, 6, 7, 8 5, 6, 7, 8 nck
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 47 [ddr3-1333 speed bins] speed bin ddr3-1333g ddr3-1333h cl-trcd-trp 8-8-8 9-9-9 symbol /cas write latency min. max. min. max. unit notes taa 12 20 13.5 20 ns trcd 12 ? 13.5 ? ns trp 12 ? 13.5 ? ns trc 48.0 ? 49.5 ? ns tras 36 9 trefi 36 9 trefi ns 9 tck (avg)@cl=5 cwl = 5 2.5 3.3 reserved reserved ns 1, 2, 3, 4, 7 cwl = 6, 7 reserved reserved reserved reserved ns 4 tck (avg)@cl=6 cwl = 5 2.5 3.3 2.5 3.3 ns 1, 2, 3, 7 cwl = 6 reserved reserved reserved reserved ns 1, 2, 3, 4, 7 cwl = 7 reserved reserved reserved reserved ns 4 tck (avg)@cl=7 cwl = 5 reserved reserved reserved reserved ns 4 cwl = 6 1.875 < 2.5 reserved reserved ns 1, 2, 3, 4, 7 cwl = 7 reserved reserved reserved reserved ns 1, 2, 3, 4 tck (avg)@cl=8 cwl = 5 reserved reserved reserved reserved ns 4 cwl = 6 1.875 < 2.5 1.875 < 2.5 ns 1, 2, 3, 7 cwl = 7 1.5 < 1.875 reserved reserved ns 1, 2, 3, 4 tck (avg)@cl=9 cwl = 5, 6 reserved reserved reserved reserved ns 4 cwl= 7 1.5 < 1.875 < 1.5 < 1.875 ns 1, 2, 3, 4 tck (avg)@cl=10 cwl = 5, 6 reserved reserved reserved reserved ns 4 cwl= 7 1.5 < 1.875 1.5 < 1.875 ns 1, 2, 3 cwl= 7 optional optional optional optional ns 5 supported cl settings 5, 6, 7, 8, 9, 10 6, 8, 9, 10 nck supported cwl settings 5, 6, 7 5, 6, 7 nck
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 48 [ddr3-1066 speed bins] speed bin ddr3-1066e ddr3-1066f ddr3-1066g cl-trcd-trp 6-6-6 7-7-7 8-8-8 symbol /cas write latency min. max. min. max. min. max. unit notes taa 11.25 20 13.125 20 15 20 ns trcd 11.25 ? 13.125 ? 15 ? ns trp 11.25 ? 13.125 ? 15 ? ns trc 48.75 ? 50.625 ? 52.50 ? ns tras 37.5 9 trefi 37.5 9 trefi 37.5 9 trefi ns 9 tck (avg)@cl=5 cwl = 5 2.5 3.3 reserved reserved reserved reserved ns 1, 2, 3, 4, 6 cwl = 6 reserved reserved reserv ed reserved reserved reserved ns 4 tck (avg)@cl=6 cwl = 5 2.5 3.3 2.5 3.3 2.5 3.3 ns 1, 2, 3, 6 cwl = 6 1.875 < 2.5 reserved reserved reserved reserved ns 1, 2, 3, 4 tck (avg)@cl=7 cwl = 5 reserved reserved reserved reserved reserved reserved ns 4 cwl = 6 1.875 < 2.5 1.875 < 2.5 reserved reserved ns 1, 2, 3, 4 tck (avg)@cl=8 cwl = 5 reserved reserved reserved reserved reserved reserved ns 4 cwl = 6 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 ns 1, 2, 3 supported cl settings 5, 6, 7, 8 6, 7, 8 6, 8 nck supported cwl settings 5, 6 5, 6 5, 6 nck [ddr3-800 speed bins] speed bin ddr3-800f ddr3-800e cl-trcd-trp 5-5-5 6-6-6 symbol /cas write latency min. max. min. max. unit notes taa 12.5 20 15 20 ns trcd 12.5 ? 15 ? ns trp 12.5 ? 15 ? ns trc 50 ? 52.5 ? ns tras 37.5 9 trefi 37.5 9 trefi ns 9 tck (avg)@cl=5 cwl = 5 2.5 3.3 reserved reserved ns 1, 2, 3, 4 tck (avg)@cl=6 cwl = 5 2.5 3.3 2.5 3.3 ns 1, 2, 3 supported cl settings 5, 6 6 nck supported cwl settings 5 5 nck notes: 1 the cl setting and cwl setting result in tc k (avg) (min.) and tck (avg) (max.) requirements. when making a selection of tck (avg), both need to be fu lfilled: requirements from cl setting as well as requirements from cwl setting. 2. tck (avg) (min.) limits: since /cas latency is not purely analog - data and strobe output are synchronized by the dll - all possible intermediate frequencies may not be guaranteed. an application should use the next smaller jedec standard tck (avg) value (2 .5, 1.875, 1.5, or 1. 25ns) when calculating cl (nck) = taa (ns) / tck (avg)(ns), rounding up to the next ?supported cl?. 3. tck (avg) (max.) limits: calculate tck (avg) + t aa (max.)/cl selected and round the resulting tck (avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875ns or 1.25ns). this result is tck (avg) (max.) corresponding to cl selected.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 49 4. ?reserved? settings are not allowed. user must program a different value. 5. 'optional' settings allow certain devices in the in dustry to support this setting, however, it is not a mandatory feature. 6. any ddr3-1066 speed bin also supports functional operation at lower frequencies as shown in the table ddr3-1066 speed bins which are not subject to producti on tests but verified by design/characterization. 7. any ddr3-1333 speed bin also supports functional operation at lower frequencies as shown in the table ddr3-1333 speed bins which is not subject to produc tion tests but verified by design/characterization. 8 any ddr3-1600 speed bin also supports functional operation at lower frequencies as shown in the table ddr3-1600 speed bins which is not subject to produc tion tests but verified by design/characterization. 9. trefi depends on operating case temperature (tc).
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 50 ac characteristics (tc = 0 c to +85 c, vdd, vddq = 1.5v 0.075v, vss, vssq = 0v) ? new units tck(avg) and nck, are introduced in ddr3. tck(avg): actual tck(avg) of the input clock under operation. nck: one clock cycle of the input cl ock, counting the actual clock edges. ac characteristics [ddr3-1600, 1333] -gl, -gn -dg, -dj data rate (mbps) 1600 1333 parameter symbol min. max. min. max. unit notes average clock cycle time tck (avg) 1250 3333 1500 3333 ps minimum clock cycle time (dll-off mode) tck (dll-off) 8 ? 8 ? ns 6 average ck high-level width tch (a vg) 0.47 0.53 0.47 0.53 tck (avg) average ck low-level width tcl (avg) 0.47 0.53 0.47 0.53 tck (avg) active to read or write command delay trcd 12.5 (gl) 13.75 (gn) ? 12 (dg) 13.5 (dj) ? ns 26 precharge command period trp 12.5 (gl) 13.75 (gn) ? 12 (dg) 13.5 (dj) ? ns 26 active to active/auto-refresh command time trc 47.5 (gl) 48.75 (gn) ? 48 (dg) 49.5 (dj) ? ns 26 active to precharge command tras 35 9 trefi 36 9 trefi ns 26 active bank a to active bank b command period trrd 6 ? 6 ? ns 26, 27 (x8) trrd 4 ? 4 ? nck 26, 27 active bank a to active bank b command period trrd ? ? 7.5 ? ns 26, 27 (x16) trrd ? ? 4 ? nck 26, 27 four active window (x8) tfaw 30 ? 30 ? ns 26 (x16) tfaw ? ? 45 ? ns 26 address and control input hold time (vih/vil (dc) levels) tih (base) 120 ? 140 ? ps 16, 23 address and control input setup time (vih/vil (ac) levels) tis (base) 45 ? 65 ? ps 16, 23 address and control input setup time (vih/vil (ac150) levels) tis (base) ac150 45 + 125 ? 65 + 125 ? ps 16, 23, 31 dq and dm input hold time (vih/vil (dc) levels) tdh (base) 45 ? 65 ? ps 17, 25 dq and dm input setup time (vih/vil (ac) levels) tds (base) 10 ? 30 ? ps 17, 25 control and address input pulse width for each input tipw 560 ? 620 ? ps 32 dq and dm input pulse width for each input tdipw 360 ? 400 ? ps 32 dq high-impedance time thz (dq) ? 225 ? 250 ps 12, 13, 14, 37 dq low-impedance time tlz (dq) ? 450 225 ? 500 250 ps 12, 13, 14, 37 dqs, /dqs high-impedance time (rl + bl/2 reference) thz (dqs) ? 225 ? 250 ps 12, 13, 14, 37 dqs, /dqs low-impedance time (rl ? 1 reference) tlz (dqs) ? 450 225 ? 500 250 ps 12, 13, 14, 37 dqs, /dqs to dq skew, per group, per access tdqsq ? 100 ? 125 ps 12, 13 /cas to /cas command delay tccd 4 ? 4 ? nck
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 51 -gl, -gn -dg, -dj data rate (mbps) 1600 1333 parameter symbol min. max. min. max. unit notes dq output hold time from dqs, /dqs tqh 0.38 ? 0.38 ? tck (avg) 12, 13, 38 dqs, /dqs rising edge output access time from rising ck, /ck tdqsck ? 225 225 ? 255 255 ps 12, 13, 37 dqs latching rising transitions to associated clock edges tdqss ? 0.27 0.27 ? 0.25 0.25 tck (avg) 24 dqs falling edge hold time from rising ck tdsh 0.18 ? 0.2 ? tck (avg) 24, 36 dqs falling edge setup time to rising ck tdss 0.18 ? 0.2 ? tck (avg) 24, 36 dqs input high pulse width tdqsh 0.45 0.55 0.45 0.55 tck (avg) 34, 35 dqs input low pulse width tdqsl 0.45 0.55 0.45 0.55 tck (avg) 33, 35 dqs output high time tqsh 0.40 ? 0.40 ? tck (avg) 12, 13, 38 dqs output low time tqsl 0.40 ? 0.40 ? tck (avg) 12, 13, 38 mode register set command cycle time tmrd 4 ? 4 ? nck mode register set command update delay tmod 15 ? 15 ? ns 27 tmod 12 ? 12 ? nck 27 read preamble trpre 0.9 ? 0.9 ? tck (avg) 1, 19, 38 read postamble trpst 0.3 ? 0.3 ? tck (avg) 11, 12, 13, 38 write preamble twpre 0.9 ? 0.9 ? tck (avg) 1 write postamble twpst 0.3 ? 0.3 ? tck (avg) 1 write recovery time twr 15 ? 15 ? ns 26 auto precharge write recovery + precharge time tdal wr + ru (trp/tck (avg)) ? wr + ru (trp/tck (avg)) ? nck multi-purpose register recovery time tmprr 1 ? 1 ? nck 29 read to write command delay (bc4mrs, bc4otf) trtw rl + tccd/2 + 2nck ? wl ? rl + tccd/2 + 2nck ? wl ? (bl8mrs, bl8otf) trtw rl + tccd + 2nck ? wl ? rl + tccd + 2nck ? wl ? internal write to read command delay twtr 7.5 ? 7.5 ? ns 18, 26, 27 twtr 4 ? 4 ? nck 18, 26, 27 internal read to precharge command delay trtp 7.5 ? 7.5 ? ns 26, 27 trtp 4 ? 4 ? nck 26, 27 active to read with auto precharge command delay trap trcd min ? trcd min ? 28 minimum cke low width for self-refresh entry to exit timing tckesr tcke (min.) +1nck ? tcke (min.) +1nck ? valid clock requirement after self- refresh entry or power-down entry tcksre 10 ? 10 ? ns 27 tcksre 5 ? 5 ? nck 27
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 52 -gl, -gn -dg, -dj data rate (mbps) 1600 1333 parameter symbol min. max. min. max. unit notes valid clock requirement before self- refresh exit or power-down exit tcksrx 10 ? 10 ? ns 27 tcksrx 5 ? 5 ? nck 27 txs trfc (min.) + 10 ? trfc (min.) + 10 ? ns 27 exit self-refresh to commands not requiring a locked dll txs 5 ? 5 ? nck 27 exit self-refresh to commands requiring a locked dll txsdll tdllk (min.) ? tdllk (min.) ? nck auto-refresh to active/auto-refresh command time trfc 110 ? 110 ? ns average periodic refresh interval (0 c tc +85 c) trefi ? 7.8 ? 7.8 s (+85 c < tc +95 c) trefi ? 3.9 ? 3.9 s tcke 5 ? 5.625 ? ns 27 cke minimum pulse width (high and low pulse width) tcke 3 ? 3 ? nck 27 txpr trfc (min.)+10 ? trfc (min.)+10 ? ns 27 exit reset from cke high to a valid command txpr 5 ? 5 ? nck 27 dll locking time tdllk 512 ? 512 ? nck power-down entry to exit time tpd tcke (min.) 9 trefi tcke (min.) 9 trefi 15 txpdll 24 ? 24 ? ns 2 exit precharge power-down with dll frozen to commands requiring a locked dll txpdll 10 ? 10 ? nck 2 txp 6 ? 6 ? ns 27 exit power-down with dll on to any valid command; exit precharge power- down with dll frozen to commands not requiring a locked dll txp 3 ? 3 ? nck 27 command pass disable/enable delay tcpded 1 ? 1 ? nck timing of last act command to power- down entry tactpden 1 ? 1 ? nck 20 timing of last pre command to power- down entry tprpden 1 ? 1 ? nck 20 timing of last read/reada command to power-down entry trdpden rl + 4 + 1 ? rl + 4 + 1 ? nck timing of last writ command to power-down entry (bl8mrs, bl8otf, bc4otf) twrpden wl + 4 + twr/tck (avg) ? wl + 4 + twr/tck (avg) ? nck 9 (bc4mrs) twrpden wl + 2 + twr/tck (avg) ? wl + 2 + twr/tck (avg) ? nck 9 timing of last writa command to power-down entry (bl8mrs, bl8otf, bc4otf) twrapden wl + 4 + wr + 1 ? wl + 4 + wr + 1 ? nck 10 (bc4mrs) twrapden wl + 2 + wr + 1 ? wl + 2 + wr + 1 ? nck 10 timing of last ref command to power- down entry trefpden 1 ? 1 ? nck 20, 21 timing of last mrs command to power-down entry tmrspden tmod (min.) ? tmod (min.) ?
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 53 odt ac electrical characte ristics [ddr3-1600, 1333] -gl, -gn -dg, -dj data rate (mbps) 1600 1333 parameter symbol min. max. min. max. unit notes rtt turn-on taon ? 225 225 ? 250 250 ps 7, 12, 37 asynchronous rtt turn-on delay (power-down with dll frozen) taonpd 2 8.5 2 8.5 ns rtt_nom and rtt_wr turn-off time from odtloff reference taof 0.3 0.7 0.3 0.7 tck (avg) 8, 12, 37 asynchronous rtt turn-off delay (power-down with dll frozen) taofpd 2 8.5 2 8.5 ns odt to power-down entry/exit latency tanpd wl ? 1.0 ? wl ? 1.0 ? nck odt turn-on latency odtlon wl ? 2 wl ? 2 wl ? 2.0 wl ? 2.0 nck odt turn-off latency odtloff wl ? 2 wl ? 2 wl ? 2.0 wl ? 2.0 nck odt latency for changing from rtt_nom to rtt_wr odtlcnw wl ? 2 wl ? 2 wl ? 2.0 wl ? 2.0 nck odt latency for change from rtt_wr to rtt_nom (bc4) odtlcwn4 ? 4 + odtloff ? 4 + odtloff nck odt latency for change from rtt_wr to rtt_nom (bl8) odtlcwn8 ? 6 + odtloff ? 6 + odtloff nck odt high time without writ command or with writ command and bc4 odth4 4 ? 4 ? nck odt high time with writ command and bl8 odth8 6 ? 6 ? nck rtt dynamic change skew tadc 0.3 0.7 0.3 0.7 tck (avg) 12, 37 power-up and reset calibration time tzqinit 512 ? 512 ? nck normal operation full calibration time tzqoper 256 ? 256 ? nck normal operation short calibration time tzqcs 64 ? 64 ? nck 30 write leveling characteristics [ddr3-1600, 1333] -gl, -gn -dg, -dj 1600 1333 parameter symbol min. max. min. max. unit notes first dqs pulse rising edge after write leveling mode is programmed twlmrd 40 ? 40 ? nck 3 dqs, /dqs delay after write leveling mode is programmed twldqsen 25 ? 25 ? nck 3 write leveling setup time from rising ck, /ck crossing to rising dqs, /dqs crossing twls 165 ? 195 ? ps write leveling hold time from rising dqs, /dqs crossing to rising ck, /ck crossing twlh 165 ? 195 ? ps write leveling output delay twlo 0 7.5 0 9 ns write leveling output error twloe 0 2 0 2 ns
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 54 ac characteristics [ddr3-1066, 800] -ac, -ae, -ag -8a, -8c data rate (mbps) 1066 800 parameter symbol min. max. min. max. unit notes clock cycle time average cl = x tck(avg) 1875 3333 2500 3333 ps minimum clock cycle time (dll-off mode) tck(dll-off) 8 ? 8 ? ns 6 average duty cycle high-level tch (a vg) 0.47 0.53 0.47 0.53 tck (avg) average duty cycle low-level tcl (avg) 0.47 0.53 0.47 0.53 tck (avg) active to read or write command delay trcd 11.25 (ac) 13.1 (ae) 15 (ag) ? 12.5 (8a) 15 (8c) ? ns 26 precharge command period trp 11.25 (ac) 13.1 (ae) 15 (ag) ? 12.5 (8a) 15 (8c) ? ns 26 active to active/auto-refresh command time trc 48.75 (ac) 50.6 (ae) 52.5 (ag) ? 50 (8a) 52.5 (8c) ? ns 26 active to precharge command tras 37.5 9 trefi 37.5 9 trefi ns 26 active bank a to active bank b command period trrd 7.5 ? 10 ? ns 26, 27 (x8) trrd 4 ? 4 ? nck 26, 27 active bank a to active bank b command period trrd 10 ? 10 ? ns 26, 27 (x16) trrd 4 ? 4 ? nck 26, 27 four active window (x8) tfaw 37.5 ? 40 ? ns 26 (x16) tfaw 50 ? 50 ? ns 26 address and control input hold time (vih/vil (dc) levels) tih (base) 200 ? 275 ? ps 16, 23 address and control input setup time (vih/vil (ac) levels) tis (base) 125 ? 200 ? ps 16, 23 address and control input setup time (vih/vil (ac150) levels) tis (base) ac150 125 + 150 ? 200 + 150 ? ps 16, 23, 31 dq and dm input hold time (vih/vil (dc) levels) tdh (base) 100 ? 150 ? ps 17, 25 dq and dm input setup time (vih/vil (ac) levels) tds (base) 25 ? 75 ? ps 17, 25 control and address input pulse width for each input tipw 780 ? 900 ? ps 32 dq and dm input pulse width for each input tdipw 490 ? 600 ? ps 32 dq high-impedance time thz (dq) ? 300 ? 400 ps 12, 13, 14, 37 dq low-impedance time tlz (dq) ? 600 300 ? 800 400 ps 12, 13, 14, 37 dqs, /dqs high-impedance time (rl + bl/2 reference) thz (dqs) ? 300 ? 400 ps 12, 13, 14, 37 dqs, /dqs low-impedance time (rl ? 1 reference) tlz (dqs) ? 600 300 ? 800 400 ps 12, 13, 14, 37 dqs, /dqs -dq skew, per group, per access tdqsq ? 150 ? 200 ps 12, 13 /cas to /cas command delay tccd 4 ? 4 ? nck dq output hold time from dqs, /dqs tqh 0.38 ? 0.38 ? tck (avg) 12, 13, 38
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 55 -ac, -ae, -ag -8a, -8c data rate (mbps) 1066 800 parameter symbol min. max. min. max. unit notes dqs, /dqs rising edge output access time from rising ck, /ck tdqsck ? 300 + 300 ? 400 + 400 ps 12, 13, 37 dqs latching rising transitions to associated clock edges tdqss ? 0.25 0.25 ? 0.25 0.25 tck (avg) 24 dqs falling edge hold time from rising ck tdsh 0.2 ? 0.2 ? tck (avg) 24, 36 dqs falling edge setup time to rising ck tdss 0.2 ? 0.2 ? tck (avg) 24, 36 dqs input high pulse width tdqsh 0.45 0.55 0.45 0.55 tck (avg) 34, 35 dqs input low pulse width tdqsl 0.45 0.55 0.45 0.55 tck (avg) 33, 35 dqs output high time tqsh 0.38 ? 0.38 ? tck (avg) 12, 13, 38 dqs output low time tqsl 0.38 ? 0.38 ? tck (avg) 12, 13, 38 mode register set command cycle time tmrd 4 ? 4 ? nck mode register set command update delay tmod 15 ? 15 ? ns 27 tmod 12 ? 12 ? nck 27 read preamble trpre 0.9 ? 0.9 ? tck (avg) 1, 19, 38 read postamble trpst 0.3 ? 0.3 ? tck (avg) 11, 12, 13, 38 write preamble twpre 0.9 ? 0.9 ? tck (avg) 1 write postamble twpst 0.3 ? 0.3 ? tck (avg) 1 write recovery time twr 15 ? 15 ? ns 26 auto precharge write recovery + precharge time tdal wr + ru (trp/tck (avg)) ? wr + ru (trp/tck (avg)) ? nck multi-purpose register recovery time tmprr 1 ? 1 ? nck 29 read to write command delay (bc4mrs, bc4otf) trtw rl + tccd/2 + 2nck ? wl ? rl + tccd/2 + 2nck ? wl ? (bl8mrs, bl8otf) trtw rl + tccd + 2nck ? wl ? rl + tccd + 2nck ? wl ? internal write to read command delay twtr 7.5 ? 7.5 ? ns 18, 26, 27 twtr 4 ? 4 ? nck 18, 26, 27 internal read to precharge command delay trtp 7.5 ? 7.5 ? ns 26, 27 trtp 4 ? 4 ? nck 26, 27 active to read with auto precharge command delay trap trcd min ? trcd min ? 28 minimum cke low width for self- refresh entry to exit timing tckesr tcke (min.) +1nck ? tcke (min.) +1nck ? valid clock requirement after self- refresh entry or power-down entry tcksre 10 ? 10 ? ns 27 tcksre 5 ? 5 ? nck 27 valid clock requirement before self- refresh exit or power-down exit tcksrx 10 ? 10 ? ns 27 tcksrx 5 ? 5 ? nck 27 exit self-refresh to commands not requiring a locked dll txs trfc (min.) + 10 ? trfc (min.) + 10 ? ns 27 txs 5 ? 5 ? nck 27
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 56 -ac, -ae, -ag -8a, -8c data rate (mbps) 1066 800 parameter symbol min. max. min. max. unit notes exit self-refresh to commands requiring a locked dll txsdll tdllk (min.) ? tdllk (min.) ? nck auto-refresh to active/auto-refresh command time trfc 110 ? 110 ? ns average periodic refresh interval (0 c tc +85 c) trefi ? 7.8 ? 7.8 s (+85 c < tc +95 c) trefi ? 3.9 ? 3.9 s cke minimum pulse width (high and low pulse width) tcke 5.625 ? 7.5 ? ns 27 tcke 3 ? 3 ? nck 27 exit reset from cke high to a valid command txpr trfc(min.)+10 ? trfc(min.)+10 ? ns 27 txpr 5 ? 5 ? nck 27 dll locking time tdllk 512 ? 512 ? nck power-down entry to exit time tpd tcke (min.) 9 trefi tcke (min.) 9 trefi 15 exit precharge power-down with dll frozen to commands requiring a locked dll txpdll 24 ? 24 ? ns 2 txpdll 10 ? 10 ? nck 2 fast exit/active precharge power-down to any command txp 7.5 ? 7.5 ? ns 27 txp 3 ? 3 ? nck 27 command pass disable/enable delay tcpded 1 ? 1 ? nck timing of last act command to power-down entry tactpden 1 ? 1 ? nck 20 timing of last pre command to power-down entry tprpden 1 ? 1 ? nck 20 timing of last read/reada command to power-down entry trdpden rl + 4 + 1 ? rl + 4 + 1 ? nck timing of last writ command to power-down entry (bl8mrs, bl8otf, bc4otf) twrpden wl + 4 + twr/tck (avg) ? wl + 4 + twr/tck (avg) ? nck 9 (bc4mrs) twrpden wl + 2 + twr/tck (avg) ? wl + 2 + twr/tck (avg) ? nck 9 timing of last writa command to power-down entry (bl8mrs, bl8otf, bc4otf) twrapden wl + 4 + wr + 1 ? wl + 4 + wr + 1 ? nck 10 (bc4mrs) twrapden wl + 2 + wr + 1 ? wl + 2 + wr + 1 ? nck 10 timing of last ref command to power-down entry trefpden 1 ? 1 ? nck 20, 21 timing of last mrs command to power-down entry tmrspden tmod (min.) ? tmod (min.) ?
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 57 odt ac electrical characte ristics [ddr3-1066, 800] -ac, -ae, -ag -8a, -8c data rate (mbps) 1066 800 parameter symbol min. max. min. max. unit notes rtt turn-on taon ?300 300 ?400 400 ps 7, 12, 37 asynchronous rtt turn-on delay (power-down with dll frozen) taonpd 2 8.5 2 8.5 ns rtt_nom and rtt_wr turn-off time from odtloff reference taof 0.3 0.7 0.3 0.7 tck (avg) 8, 12, 37 odt turn-off (power-down mode) taofpd 2 8.5 2 8.5 ns odt to power-down entry/exit latency tanpd wl ? 1.0 ? wl ? 1.0 ? nck odt turn-on latency odtlon wl ? 2.0 wl ? 2.0 wl ? 2.0 wl ? 2.0 nck odt turn-off latency odtloff wl ? 2.0 wl ? 2.0 wl ? 2.0 wl ? 2.0 nck odt latency for changing from rtt_nom to rtt_wr odtlcnw wl ? 2.0 wl ? 2.0 wl ? 2.0 wl ? 2.0 nck odt latency for change from rtt_wr to rtt_nom (bc4) odtlcwn4 ? 4 + odtloff ? 4 + odtloff nck odt latency for change from rtt_wr to rtt_nom (bl8) odtlcwn8 ? 6 + odtloff ? 6 + odtloff nck odt high time without writ command or with writ command and bc4 odth4 4 ? 4 ? nck odt high time with writ command and bl8 odth8 6 ? 6 ? nck rtt dynamic change skew tadc 0.3 0.7 0.3 0.7 tck (avg) 12, 37 power-up and reset calibration time tzqinit 512 ? 512 ? nck normal operation full calibration time tzqoper 256 ? 256 ? nck normal operation short calibration time tzqcs 64 ? 64 ? nck 30 write leveling characteristics [ddr3-1066, 800] -ac, -ae, -ag -8a, -8c 1066 800 parameter symbol min. max. min. max. unit notes first dqs pulse rising edge after write leveling mode is programmed twlmrd 40 ? 40 ? nck 3 dqs, /dqs delay after write leveling mode is programmed twldqsen 25 ? 25 ? nck 3 write leveling setup time from rising ck, /ck crossing to rising dqs, /dqs crossing twls 245 ? 325 ? ps write leveling hold time from rising dqs, /dqs crossing to rising ck, /ck crossing twlh 245 ? 325 ? ps write leveling output delay twlo 0 9 0 9 ns write leveling output error twloe 0 2 0 2 ns
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 58 notes for ac electrical characteristics notes: 1. actual value dependent upon meas urement level definitions that are tbd. 2. commands requiring locked dll are: read (and reada) and synchronous odt commands. 3. the max values are system dependent. 4. wr as programmed in mode register. 5. value must be rounded-up to next integer value. 6. there is no maximum cycle time limit besides the need to satisfy the refresh interval, trefi. 7. odt turn on time (min.) is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time (max.) is when the odt resistance is fully on. both are measured from odtlon. 8. odt turn-off time (min.) is when the device starts to turn-off odt resistance. odt turn-off time (max.) is when the bus is in high impedance. both are measured from odtloff. 9. twr is defined in ns, for calculation of twrpden it is necessary to round up twr/tck to the next integer. 10. wr in clock cycles as programmed in mr0. 11. the maximum read postamble is bound by tdqsck(min.) plus tqsh(min.) on the left side and thz(dqs)(max.) on the right side. 12. output timing deratings are rela tive to the sdram input clock. w hen the device is operated with input clock jitter, this parameter needs to be derated by tbd. 13. value is only valid for ron34. 14. single ended signal parameter. refer to the section of tlz (dqs), tlz (dq), th z (dqs), thz (dq) notes for definition and measurement method. 15. trefi depends on operating case temperature (tc). 16. tis(base) and tih(base) values are for 1v/ns command/address single-ended slew rate and 2v/ns ck, /ck differential slew rate. note for dq and dm signals, vref(dc) = vrefdq(dc). for input only pins except /reset, vref(dc) = vrefca(dc). see addr ess / command setup, hold and derating section 17. tds(base) and tdh(base) values are for 1v/n s dq single-ended slew rate and 2v/ns dqs, /dqs differential slew rate. note for dq and dm signals, vref(dc) = vrefdq(dc). for input only pins except /reset, vref(dc) = vrefca(dc). see data set up, hold and slew ra te derating section. 18. start of internal write tr ansaction is definited as follows: for bl8 (fixed by mrs and on- the-fly): rising clock edge 4 clock cycles after wl. for bc4 (on-the-fly): rising clock edge 4 clock cycles after wl. for bc4 (fixed by mrs): rising clock edge 2 clock cycles after wl. 19. the maximum read preamble is bound by tlz(dq s)(min.) on the left side and tdqsck(max.) on the right side. 20. cke is allowed to be registered low while operatio ns such as row activation, precharge, auto precharge or refresh are in progress, but power-down idd spec will not be applied until finishing those operations. 21. although cke is allowed to be registered low afte r a refresh command once trefpden(min.) is satisfied, there are cases where additional time such as txpdll(min.) is also required. see figure power-down entry/exit clarifica tions - case 2. 22. tjit(duty) = { 0.07 tck(avg) ? [(0.5 - (min (tch(avg), tcl(avg))) tck(avg)] }. for example, if tch/tcl was 0.48/0. 52, tjit(duty) would calculate out to 125ps for ddr3-800. the tch(avg) and tcl(avg) val ues listed must not be exceeded. 23. these parameters are measur ed from a command/address signal (cke, /cs, /ras, /cas, /we, odt, ba0, a0, a1, etc.) transition edge to its respective cl ock signal (ck, /ck) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tj it(per), tjit(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches t he command/address. that is , these parameters should be met whether clock jitter is present or not. 24 these parameters are measured fr om a data strobe signal ((l/u/t)dqs, /dqs) crossing to its respective clock signal (ck, /ck) crossing. the spec values ar e not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as thes e are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not. 25. these parameters are measured fr om a data signal ((l/u)dm, (l/u)dq0, (l/u)dq1, etc.) transition edge to its respective data strobe signal ((l/u/t)dqs/dqs) crossing.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 59 26. for these parameters, the ddr3 sdram device is characterized and verified to support tnparam [nck] = ru{tparam [ns] / tck(avg)}, which is in clock cycles, assu ming all input clock jitter specifications are satisfied. for example, the device will support tnrp = ru{trp / tc k(avg)}, which is in clock cycles, if all input clock jitter specifications are met. this means: for ddr 3-800 6-6-6, of which trp = 15ns, the device will support tnrp =ru{trp / tck(avg)} = 6, i.e. as long as the input clock jitter specifications are met, precharge command at tm and active co mmand at tm+6 is valid even if (tm+6 ? tm) is less than 15ns due to input clock jitter. 27. these parameters should be the larger of the tw o values, analog (ns) and number of clocks (nck). 28 the tras lockout circuit internally delays the precharge operation until the array restore operation has been completed so that the auto precharge command may be issued with any read or write command. 29 defined between end of mpr read burst and mrs which reloads mpr or disables. 30 one zqcs command can effectively correct a minimum of 0.5% (zqcorrection) of ron and rtt impedance error within 64nck for all speed bins assu ming the maximum sensitiv ities specified in the ?output driver voltage and temperature sensitivity? and ?odt voltage and tem perature sensitivity? tables. the appropriate interval between zqcs co mmands can be determined from these tables and other application-s pecific parameters. one method for calculating the interval between zq cs commands, given the temperature (tdriftrate) and voltage (vdriftrate) drift rates that the sdram is subject to in the applic ation, is illustrated. the interval could be defined by the following formula:

where tsens = max.(drttdt, drondtm) and vs ens = max.(drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5%/ c, vsens = 0.15%/mv, tdriftrate = 1 c/sec and vdriftrate = 15mv/sec, then the interv al between zqcs commands is calculated as:
31 the tis(base) ac150 specificati ons are adjusted from the tis(base) specification by adding an additional 100ps of derating to accommodate for the lower al ternate threshold of 150mv and another 25ps to account for the earlier reference point [(175mv ? 150mv)/1v/ns]. 32 pulse width of a input signal is defined as the width between the first crossing of vref(dc) and the consecutive crossing of vref(dc). 33 tdqsl describes the instantaneous differential input low pulse width on dqs ? /dqs, as measured from one falling edge to the next consecutive rising edge. 34 tdqsh describes the instantaneous differential input high pulse width on dqs ? /dqs, as measured from one rising edge to the next consecutive falling edge. 35 tdqsh,act + tdqsl,act = 1tck,act ; with txyz,act being the actual measured value of the respective timing parameter in the application. 36 tdsh,act + tdss,act = 1tck,act ; with txyz,act being the actual measured value of the respective timing parameter in the application. 37 when the device is operated with input clock jitte r, this parameter needs to be derated by the actual terr(mper),act of the input clock, where 2 m 12. (output deratings are re lative to the sdram input clock.) for example, if the measured jitter in to a ddr3-800 sdram has terr(mper),act,min = ? 172ps and terr(mper),act,max = +193ps, then tdqsck,min(derated) = tdqsck,min ? terr(mper),act,max = ? 400ps ? 193ps = ? 593ps and tdqsck,max(derated) =tdqsck,max ? terr(mper),act,min = 400ps + 172ps = +572ps. similarly, tlz(dq) forddr3 -800 derates to tlz(dq),min(derated) = ? 800ps ? 193ps = ? 993ps and tlz(dq),max(derated) = 400ps + 172ps = +572ps. note that terr(mper),act,min is the minimum measured value of terr(nper) where 2 n 12, and terr(mper),act,max is the maximum measured value of terr(nper) where 2 n 12. 38 when the device is operated with input clock jitte r, this parameter needs to be derated by the actual tjit(per),act of the input clo ck. (output deratings are relati ve to the sdram input clock.) for example, if the measured jitter into a ddr3-8 00 sdram has tck(avg),act = 2500ps, tjit(per),act,min = ? 72ps and tjit(per),act,max = +93ps, then trpre,min( derated) = trpre,min + tjit(per),act,min = 0.9 tck(avg),act + tjit(per),act,min = 0.9 2500ps ? 72ps = +2178ps. similarly, tqh,min(derated) = tqh,min + tjit(per),act,min = 0.38 tck(avg),act + tjit(per),act,min = 0.38 2500ps ? 72ps = + 878ps.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 60 clock jitter [ddr3-1600, 1333] -gl, -gn -dg, -dj data rate (mbps) 1600 1333 parameter symbol min. max. min. max. unit notes average clock period tck (avg) 1250 3333 1500 3333 ps 1 absolute clock period tck (abs) tck(avg)min + tjit(per)min tck(avg)max+ tjit(per)max tck(avg)min + tjit(per)min tck(avg)max+ tjit(per)max ps 2 clock period jitter tjit (per) ? 70 70 ? 80 80 ps 6 clock period jitter during dll locking period tjit (per, lck) ? 60 60 ? 70 70 ps 6 cycle to cycle period jitter tjit (cc) ? 140 ? 160 ps 7 cycle to cycle clock period jitter during dll locking period tjit (cc, lck) ? 120 ? 140 ps 7 cumulative error across 2 cycles terr (2per) ? 103 103 ? 118 118 ps 8 cumulative error across 3 cycles terr (3per) ? 122 122 ? 140 140 ps 8 cumulative error across 4 cycles terr (4per) ? 136 136 ? 155 155 ps 8 cumulative error across 5 cycles terr (5per) ? 147 147 ? 168 168 ps 8 cumulative error across 6 cycles terr (6per) ? 155 155 ? 177 177 ps 8 cumulative error across 7 cycles terr (7per) ? 163 163 ? 186 186 ps 8 cumulative error across 8 cycles terr (8per) ? 169 169 ? 193 193 ps 8 cumulative error across 9 cycles terr (9per) ? 175 175 ? 200 200 ps 8 cumulative error across 10 cycles terr (10per) ? 180 180 ? 205 205 ps 8 cumulative error across 11 cycles terr (11per) ? 184 184 ? 210 210 ps 8 cumulative error across 12 cycles terr (12per) ? 188 188 ? 215 215 ps 8 cumulative error across n = 13, 14?49, 50 cycles terr (nper) terr (nper) min. = (1+0.68in(n)) x tjit(per) min terr (nper) max. = (1+0.68in(n)) x tjit(per) max ps 9 average high pulse width tch (avg) 0.47 0.53 0.47 0.53 tck (avg) 3 average low pulse width tcl (avg) 0.47 0.53 0.47 0.53 tck (avg) 4 absolute clock high pulse width tch (abs) 0.43 ? 0.43 ? tck (avg) 10, 11 absolute clock low pulse width tcl (abs) 0.43 ? 0.43 ? tck (avg) 10, 12 duty cycle jitter tjit (duty) ? ? ? ? ps 5
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 61 clock jitter [ddr3-1066, 800] -ac, -ae, -ag -8a, -8c data rate (mbps) 1066 800 parameter symbol min. max. min. max. unit notes average clock period tck (avg) 1875 3333 2500 3333 ps 1 absolute clock period tck (abs) tck(avg)min + tjit(per)min tck(avg)max+ tjit(per)max tck(avg)min + tjit(per)min tck(avg)max+ tjit(per)max ps 2 clock period jitter tjit (per) ? 90 90 ? 100 100 ps 6 clock period jitter during dll locking period tjit (per, lck) ? 80 80 ? 90 90 ps 6 cycle to cycle period jitter tjit (cc) ? 180 ? 200 ps 7 cycle to cycle clock period jitter during dll locking period tjit (cc, lck) ? 160 ? 180 ps 7 cumulative error across 2 cycles terr (2per) ? 132 132 ? 147 147 ps 8 cumulative error across 3 cycles terr (3per) ? 157 157 ? 175 175 ps 8 cumulative error across 4 cycles terr (4per) ? 175 175 ? 194 194 ps 8 cumulative error across 5 cycles terr (5per) ? 188 188 ? 209 209 ps 8 cumulative error across 6 cycles terr (6per) ? 200 200 ? 222 222 ps 8 cumulative error across 7 cycles terr (7per) ? 209 209 ? 232 232 ps 8 cumulative error across 8 cycles terr (8per) ? 217 217 ? 241 241 ps 8 cumulative error across 9 cycles terr (9per) ? 224 224 ? 249 249 ps 8 cumulative error across 10 cycles terr (10per) ? 231 231 ? 257 257 ps 8 cumulative error across 11 cycles terr (11per) ? 237 237 ? 263 263 ps 8 cumulative error across 12 cycles terr (12per) ? 242 242 ? 269 269 ps 8 cumulative error across n=13, 14?49,50 cycles terr (nper) terr (nper) min. = (1+0.68in(n)) x tjit(per) min terr (nper) max. = (1+0.68in(n)) x tjit(per) max ps 9 average high pulse width tch (avg) 0.47 0.53 0.47 0.53 tck (avg) 3 average low pulse width tcl (avg) 0.47 0.53 0.47 0.53 tck (avg) 4 absolute clock high pulse width tch (abs) 0.43 ? 0.43 ? tck (avg) 10, 11 absolute clock low pulse width tcl (abs) 0.43 ? 0.43 ? tck (avg) 10, 12 duty cycle jitter tjit (duty) ? ? ? ? ps 5 notes: 1. tck (avg) is calculated as the average clo ck period across any consecutive 200cycle window, where each clock period is calculated from rising edge to rising edge. n j = 1 tck j n n = 200 2. tck (abs) is the absolute clock per iod, as measured from one rising e dge to the next consecutive rising edge. tck (abs) is not subject to production test. 3. tch (avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses. n j = 1 tch j (n t ck(avg) ) n = 200
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 62 4. tcl (avg) is defined as the average low pulse widt h, as calculated across any consecutive 200 low pulses. n j = 1 tcl j (n t ck(avg) ) n = 200 5. tjit (duty) is defined as the cumulative set of tc h jitter and tcl jitter. tch jitte r is the largest deviation of any single tch from tch (avg). tcl jitter is the la rgest deviation of any single tcl from tcl (avg). tjit (duty) is not subject to production test. tjit (duty) = min./max. of {tjit (ch), tjit (cl)}, where: tjit (ch) = {tch j - tch (avg) where j = 1 to 200} tjit (cl) = {tcl j - tcl (avg) where j = 1 to 200} 6. tjit (per) is defined as the largest dev iation of any single tck from tck (avg). tjit (per) = min./max. of { tck j ? tck (avg) where j = 1 to 200} tjit (per) defines the single period jitter when the d ll is already locked. tjit (per, lck) uses the same definition for single period jitter, during the dll locki ng period only. tjit (per) and tjit (per, lck) are not subject to production test. 7. tjit (cc) is defined as the abs olute difference in clock period between two consecutive clock cycles: tjit (cc) = max. of {tck j+1 - tck j } tjit (cc) is defines the cycle wh en the dll is already locked. tjit (c c, lck) uses the same definition for cycle-to-cycle jitter, during the dll locking period only . tjit (cc) and tjit (cc, lck) are not subject to production test. 8. terr (nper) is defined as the cumulative error ac ross n multiple consecutive cycles from tck (avg). terr (nper) is not subject to production test. 9 n = from 13 cycles to 50 cycles. this row defines 38 parameters. 10. these parameters are specified per their average values, however it is understood that the following relationship between the average timing and the abs olute instantaneous timing hold at all times. (minimum and maximum of spec values are to be used for calculations in the table below.) parameter symbol min. max. unit absolute clock period tck (abs) tck (avg), min. + tjit (per),min. tck (avg), max. + tjit (per),max. ps absolute clock high pulse width tch (abs) tch (avg), min. tck (avg),min. + tjit (duty),min. tch (avg), max. tck (avg),max. + tjit (duty),max. ps absolute clock low pulse width tcl (abs) tcl (avg), min. tck (avg),min. + tjit (duty),min. tcl (avg), max. tck (avg),max. + tjit (duty),max. ps 11 tch (abs) is the absolute inst antaneous clock high pulse width, as measured from one rising edge to the following falling edge. 12 tcl(abs) is the absolute instant aneous clock low pulse width, as measured from one falling edge to the following rising edge.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 63 block diagram bank 7 bank 6 bank 5 bank 4 address, ba0, ba1, ba2 /cs /ras /cas /we command decoder input & output buffer latch circuit data control circuit column decoder row decoder memory cell array bank 0 sense amp. bank 1 bank 2 bank 3 control logic column address buffer and burst counter row address buffer and refresh counter mode register clock generator dq ck /ck cke dqs, /dqs dm dll ck, /ck tdqs, /tdqs odt
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 64 pin function ck, /ck (input pins) ck and /ck are differential clock inputs. all address and c ontrol input signals are sampled on the crossing of the positive edge of ck and negative edge of /ck. output (read) data is referenced to the crossings of ck and /ck (both directions of crossing). /cs (input pin) all commands are masked when /cs is registered high. /cs provides for external rank selection on systems with multiple ranks. /cs is considered part of the command code. /ras, /cas, /we (input pins) /ras, /cas and /we (along with /cs) define the command being entered. a0 to a13 (input pins) provided the row address for active commands and the co lumn address for read/write commands to select one location out of the memory array in the respective bank. (a10(ap) and a12(/bc) have additional functions, see below) the address inputs also provide t he op-code during mode register set commands. [address pins table] address (a0 to a13) part number page size row address (ra) column address (ca) note edj1108babg 1kb ax0 to ax13 ay0 to ay9 edj1116babg 2kb ax0 to ax12 ay0 to ay9 1 note: a13 pin is nc for x16 organization. a10(ap) (input pin) a10 is sampled during read/write commands to determine whether auto precharge should be performed to the accessed bank after the read/write operation. (h igh: auto precharge; low: no auto precharge) a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 = low) or all banks (a10 = high). if only one bank is to be prec harged, the bank is selected by bank addresses (ba). a12(/bc) (input pin) a12 is sampled during read and write commands to determi ne if burst chop (on-the-fly) will be performed. (a12 = high: no burst chop, a12 = low: burs t chopped.) see command truth table for details. ba0 to ba2 (input pins) ba0, ba1 and ba2 define to which bank an active, read, write or precharge command is being applied. ba0 and ba1 also determine which mode register (mr0 to mr3) is to be accessed during a mrs cycle. [bank select signal table] ba0 ba1 ba2 bank 0 l l l bank 1 h l l bank 2 l h l bank 3 h h l bank 4 l l h bank 5 h l h bank 6 l h h bank 7 h h h remark: h: vih. l: vil.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 65 cke (input pin) cke high activates, and cke low deactivates, internal cl ock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self-refr esh operation (all banks idle), or active power-down (row active in any bank). cke is asynchronous for se lf-refresh exit. after vref has become stable during the power-on and initialization sequence, it must be maintained for proper operat ion of the cke receiver. for proper self-refresh entry and exit, vref must be maintained to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, /ck, odt and cke are disabled during power-down. input buffers, excluding cke, are disabled during self-refresh. dm, dmu, dml (input pins) dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. for 8 configuration, the function of dm or tdqs, /tdqs is enabled by mode register a11 setting in mr1. dq, dqu, dql (input/output pins) bi-directional data bus. dqs, /dqs, dqsu, /dqsu, dqsl, /dqsl (input/output pins) output with read data, input with write data. edge-ali gned with read data, center-aligned with write data. the data strobe dqs is paired with differential signal /dqs to provide differential pair signaling to the system during reads and writes. tdqs, /tdqs (output pins) tdqs and /tdqs is applicable for 8 configuration only. when enabled via mode register a11 = 1 in mr1, dram will enable the same termination resistance function on td qs, /tdqs as is applied to dqs, /dqs. when disabled via mode register a11 = 0 in mr1, dm/tdqs will pr ovide the data mask function and /tdqs is not used. in 16 configuration, the tdqs f unction must be disabled via mode register a11 = 0 in mr1. /reset (input pin) /reset is a cmos rail to rail signal with dc high and lo w at 80% and 20% of vdd (1.20v for dc high and 0.30v for dc low). it is negative active signal (active low) and is referred to gnd. there is no termination required on this signal. it will be heavily load ed across multiple chips. /reset is destructive to data contents. odt (input pins) odt (registered high) enables termination resistance inte rnal to the ddr3 sdram. when enabled, odt is only applied to each dq, dqs, /dqs, dm/tdqs, nu(/tdqs) (when tdqs is enabled via mode register a11 = 1 in mr1) signal for 4/ 8 configuration. for 16 configuration odt is applied to each dq, dqsu, /dqsu, dqsl, /dqsl, dmu, and dml signal. the odt pin will be ignored if the mode register (mr1) is programmed to disable odt. zq (supply) reference pin for zq calibration. vdd, vss, vddq, vssq (power supply) vdd and vss are power supply pins for internal circuits . vddq and vssq are power supply pins for the output buffers. vrefca, vrefdq (power supply) reference voltage
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 66 command operation command truth table the ddr3 sdram recognizes the following commands spec ified by the /cs, /ras, /cas, /we and address pins. cke function symbol previous cycle current cycle /cs /ras /cas /we ba0 to ba2 a12 (/bc) a10 (ap) address notes mode register set mrs h h l l l l ba op-code auto-refresh ref h h l l l h v v v v self-refresh entry self h l l l l h v v v v 6, 8, 11 self-refresh exit srex l h h 6, 7, 8, 11 l h l h h h v v v v single bank precharge pre h h l l h l ba v l v precharge all banks pall h h l l h l v v h v bank activate act h h l l h h ba ra 12 write (fixed bl) writ h h l h l l ba v l ca write (bc4, on the fly) wrs4 h h l h l l ba l l ca write (bl8, on the fly) wrs8 h h l h l l ba h l ca write with auto precharge (fixed bl) writa h h l h l l ba v h ca write with auto precharge (bc4, on the fly) wras4 h h l h l l ba l h ca write with auto precharge (bl8, on the fly) wras8 h h l h l l ba h h ca read (fixed bl) read h h l h l h ba v l ca read (bc4, on the fly) rds4 h h l h l h ba l l ca read (bl8, on the fly) rds8 h h l h l h ba h l ca read with auto precharge (fixed bl) reada h h l h l h ba v h ca read with auto precharge (bc4, on the fly) rdas4 h h l h l h ba l h ca read with auto precharge (bl8, on the fly) rdas8 h h l h l h ba h h ca no operation nop h h l h h h v v v v 9 device deselect desl h h h 10 power-down mode entry pden h l h 5, 11 h l l h h h v v v v power-down mode exit pdex l h h 5, 11 l h l h h h v v v v zq calibration long zqcl h h l h h l h zq calibration short zqcs h h l h h l l remark: h = vih. l = vil. = don't care (defined or undefined (including floating around vref)) logic level. v = vih or vil (defined logic level). ba = bank addresses. ra = row address. ca = column address. /bc = burst chop.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 67 notes: 1. all ddr3 commands are defined by states of /c s, /ras, /cas, /we and cke at the rising edge of the clock. the most significant bit (msb) of ba, ra , and ca are device density and configuration dependent. 2. /reset is an active low asynchronous signal that must be driven high during normal operation 3. bank addresses (ba) determine which bank is to be operated upon. for mrs, ba selects an mode register. 4. burst reads or writes cannot be terminated or interrupted and fixed/on the fly bl will be defined by mrs. 5. the power-down mode does not perform any refresh operations. 6. the state of odt does not affe ct the states described in this tabl e. the odt function is not available during self-refresh. 7. self-refresh exit is asynchronous. 8. vref (both vrefdq and vrefca) must be maintained during self-refresh operation. 9. the no operation command (nop) should be used in cases when the ddr3 sdram is in an idle or a wait state. the purpose of the nop command is to prevent the ddr3 sdram from registering any unwanted commands between operations. a nop command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 10. the desl command performs t he same function as a nop command. 11. refer to the cke truth table for more detail with cke transition. 12. no more than 4 banks may be activated in a ro lling tfaw window. converting to clocks is done by dividing tfaw (ns) by tck (ns) and rounding up to next integer value. as an example of the rolling window, if (tfaw/tck) rounds up to 10 clocks, and an activate command is issued in clock n, no more than three further activate commands may be issued in clock n+1 through n+9. no operation command [nop] the no operation command (nop) should be used in cases wh en the ddr3 sdram is in an idle or a wait state. the purpose of the nop command is to prevent the ddr3 sdram from registering any unwanted commands between operations. a nop command will not terminate a previous operation that is still exec uting, such as a burst read or write cycle. the no operation (nop) command is used to instruct the selected ddr3 sdra m to perform a nop (/cs low, /ras, /cas, /we high). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. device deselect command [desl] the deselect function (/cs high) prevents new comm ands from being executed by the ddr3 sdram. the ddr3 sdram is effectively deselected. operatio ns already in progress are not affected. mode register set command [mr0 to mr3] the mode registers are loaded via row address inputs. see mode register descriptions in the programming the mode register section. the mode register set co mmand can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tmrd is met. bank activate command [act] this command is used to open (or activate) a row in a particu lar bank for a subsequent access. the values on the ba inputs select the bank, and the address provided on row add ress inputs selects the row. this row remains active (or open) for accesses until a precharge command is issu ed to that bank. a precharge command must be issued before opening a different row in the same bank. note: no more than 4 banks may be activated in a rolling tfaw window. converting to clocks is done by dividing tfaw (ns) by tck (ns) and rounding up to next integer value. as an example of the rolling window, if (tfaw/tck) rounds up to 10 clocks, and an activate command is issued in clock n, no more than three further activate commands may be issued in clock n+1 through n+9.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 68 read command [read, rds4, rds8, reada, rdas4, rdas8] the read command is used to initiate a burst read access to an active row. the values on the ba inputs select the bank, and the address provided on column address inputs sele cts the starting column location. the value on input a10 determines whether or not auto precharge is used. if aut o precharge is selected, the row being accessed will be precharged at the end of the read burs t; if auto precharge is not selected, t he row will remain open for subsequent accesses. write command [writ, wrs4, wrs8, writa, wras4, wras8] the write command is used to initiate a burst write access to an active row. the values on the ba inputs select the bank, and the address provided on column address inputs sele cts the starting column location. the value on input a10 determines whether or not auto precharge is used. if aut o precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dq is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to memory; if the dm signal is registered high, the corresp onding data inputs will be ignored, and a write will not be executed to that by te/column location. precharge command [pre, pall] the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a spec ified time (trp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in t he case where only one bank is to be precharged, inputs ba select the bank. otherwise ba are treated as "don't care." once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command will be treated as a nop if ther e is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. auto precharge command [reada, writa] before a new row in an active bank can be opened, the ac tive bank must be precharged using either the precharge command or the auto precharge function. when a read or a write command is given to the ddr3 sdram, the /cas timing accepts one extra address, column address a10, to a llow the active bank to automat ically begin precharge at the earliest possible moment during the bur st read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is execut ed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write command is issued, then the auto precharge function is engaged. during auto precharge, a read command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is /cas la tency (cl) clock cycles befor e the end of the read burst. (this timing is equal to the rising edge which is (al* + bl/2) cycles later from the read with auto precharge command.) auto precharge can also be implemented during write co mmands. the precharge operation engaged by the auto precharge command will not begin until the la st data of the burst wr ite sequence is properly stored in the memory array. this feature allows the prec harge operation to be partially or completely hidden during burst read cycles (dependent upon /cas latency) thus improving system performance for random data access. the tras lockout circuit internally delays the precharge operation until the array restore ope ration has been completed so that the auto precharge command may be issued with any read or write command. note: al (additive latenc y), refer to posted /cas de scription in the register definition section. auto-refresh command [ref] auto-refresh is used during normal operation of the ddr3 sdram and is analogous to /cas-before-/ras (cbr) refresh in fpm/edo dram. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a "don't care" during an auto-refresh command. a maximum of eight auto-refresh commands can be posted to any given ddr3, meaning that the maximum absolute interval between any auto-refresh comma nd and the next auto-refresh command is 9 trefi. this maximum absolute interval is to allow ddr3 output drivers and inte rnal terminators to automatically recalibrate compensating for voltage and temperature changes.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 69 self-refresh command [self] the self-refresh command can be used to retain data in the ddr 3, even if the rest of the system is powered down. when in the self-refresh mode, the ddr 3 retains data without external clocking. the self-refresh command is initiated like an auto-refresh command except cke is dis abled (low). the dll is automatically disabled upon entering self-refresh and is autom atically enabled and reset upon exiting self -refresh. the active termination is also disabled upon entering self-refresh and enabled upon exiting se lf-refresh. (512 clock cycles must then occur before a read command can be issued). input signals except cke ar e "don't care" during self-refresh. the procedure for exiting self-refresh requires a seque nce of commands. first, ck and /ck must be stable prior to cke going back high. once cke is high, the ddr3 must have nop comm ands issued for txsdll because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh, dll requirements and out-put calibration is to apply nops for 512 clock cycles before applying any other command to allow the dll to lock and the output drivers to recalibrate. zq calibration command [zqcl, zqcs] zq calibration command (short or long) is used to calibrate dram ron and odt values over pvt. zq calibration long (zqcl) command is used to perform the initial calibration during power-up initialization sequence. zq calibration short (zqcs) command is used to perform pe riodic calibrations to account for vt variations. all banks must be precharged and trp met before zqcl or zqcs commands are issued by the controller. zq calibration commands can also be issued in paralle l to dll lock time when coming out of self-refresh.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 70 cke truth table cke current state* 2 previous cycle (n-1)* 1 current cycle (n) *1 command (n) *3 /cs, /ras, /cas, /we operation (n) *3 notes power-down l l maintain power-down 14, 15 l h desl or nop power-down exit 11, 14 self-refresh l l maintain self-refresh 15, 16 l h desl or nop self-refresh exit 8, 12, 16 bank active h l desl or nop active power-down entry 11, 13, 14 reading h l desl or nop power-down entry 11, 13, 14, 17 writing h l desl or nop power-down entry 11, 13, 14, 17 precharging h l desl or nop power-down entry 11, 13, 14, 17 refreshing h l desl or nop precharge power-down entry 11 all banks idle h l desl or nop precharge power-down entry 11, 13, 14, 18 h l refresh self-refresh entry 9, 13, 18 any state other than listed above h h refer to the command truth table 10 remark: h = vih. l = vil. = don?t care notes: 1. cke (n) is the logic st ate of cke at clock edge n; cke (n ? 1) is the state of cke at the previous clock edge. 2. current state is the st ate of the ddr3 sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock e dge n, and operation (n) is a result of command (n). odt is not included here. 4. all states and sequences not sh own are illegal or reserved unless explicitly described elsewhere in this document. 5. the state of odt does not affect the states described in this table. the odt function is not available during self-refresh. 6. cke must be registered with the same value on tc ke (min.) consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the tcke (min.) clocks of registration. thus, after any cke transition, cke may not transition from its valid level during the time period of tis + tcke (min.) + tih. 7. desl and nop are defined in the command truth table. 8. on self-refresh exit, desl or nop commands must be issued on every clock edge occurring during the txs period. read or odt command may be issued only after txsdll is satisfied. 9. self-refresh mode can only be enter ed from the all banks idle state. 10. must be a legal command as defined in the command truth table. 11. valid commands for power-down entry and exit are nop and desl only. 12. valid commands for self-refresh exit are nop and desl only. 13. self-refresh can not be entered wh ile read or write operations, (exten ded) mode register set operations or precharge operations are in progre ss. see section power-down and self-refresh command for a detailed list of restrictions. 14. the power-down does not perform any refresh operations. 15. ? ? means ?don?t care? (including floating around vref) in self-refresh and power-down. it also applies to address pins. 16. vref (both vrefdq and vrefca) must be maintained during self-refresh operation. 17. if all banks are closed at the c onclusion of the read, write or pr echarge command, the precharge power- down is entered, otherwise active power-down is entered. 18. idle state means that all banks are closed (trp, tdal, etc. satisfied), no data bursts are in progress. cke is high and all timings from previous operation are satisfied (tmrd, tmod, trfc, tzqinit, tzqoper, tzqcs, etc.) as well as all self-refresh exit and power-down exit parameters are satisfi ed (txs, txp, txpdll, etc).
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 71 simplified state diagram power on reset procedure power applied reset from any state initialization zq calibration idle activating mrs, mpr, write leveling self refresh refreshing mrs self selfx cke_l cke_l cke_l ref pden pdex act precharge power down active power down reading writing bank active read read writ writ precharging pden pdex reading writing reada writa reada reada writa writ writa pre, pall automatic sequence command sequence pre, pall pre, pall read zqcl zqcs
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 72 reset and initialization procedure power-up and initialization sequence 1. apply power (/reset is recommended to be maintained below 0.2 vdd, (all other inputs may be undefined). ) /reset needs to be maintained for minimum 200 s with stable power. cke is pulled low anytime before /reset being de-asserted (min. time 10ns). the power voltage ramp time between 300mv to vdd (min.) must be no greater than 200ms; and duri ng the ramp, vdd > vddq and (vdd ? vddq) < 0.3v. ? vdd and vddq are driven from a single power converter output and ? the voltage levels on all pins other than vdd, vddq, vss, vssq must be less than or equal to vddq and vdd on one side and must be larger than or equal to vssq and vss on the other side. in addition, vtt is limited to 0.95v max once power ramp is finished, and ? vref tracks vddq/2. or ? apply vdd without any slope reversal before or at the same time as vddq. ? apply vddq without any slope reversal before or at the same time as vtt and vref. ? the voltage levels on all pins other than vdd, vddq, vss, vssq must be less than or equal to vddq and vdd on one side and must be larger than or equal to vssq and vss on the other side. 2. after /reset is de-asserted, wait for another 500 s until cke become active. during this time, the dram will start internal state initialization; this wi ll be done independently of external clocks. 3. clocks (ck, /ck) need to be started and stabilized for at least 10ns or 5tck (which is larger) before cke goes active. since cke is a synchronous signal, the correspond ing set up time to clock (tis) must be met. also a nop or desl command must be registered (with tis set up ti me to clock) before cke goes active. once the cke registered ?high? after reset, cke needs to be continuo usly registered high until th e initialization sequence is finished, including expiration of tdllk and tzqinit. 4. the ddr3 sdram will keep its on-die termination in high-impedance state during /reset being asserted at least until cke being registered high. therefore, the odt signal may be in undefined state until tis before cke being registered high. after that, the odt signal must be kept inactive (low) until t he power-up and initialization sequence is finished, including expiration of tdllk and tzqinit. 5. after cke being registered high, wait minimum of tx pr, before issuing the first mrs command to load mode register. (txpr = max. (txs ; 5 tck) 6. issue mrs command to load mr2 with all application settings. (to issue mrs command for mr2, provide low to ba0 and ba2, high to ba1.) 7. issue mrs command to load mr3 with all application settings. (to issue mrs command for mr3, provide low to ba2, high to ba0 and ba1.) 8. issue mrs command to load mr1 with all applicat ion settings and dll enabled. (to issue dll enable command, provide low to a0, high to ba0 and low to ba1 and ba2). 9. issue mrs command to load mr0 with all application settings and dll reset. (to issue dll reset command, provide high to a8 and low to ba0 to ba2). 10. issue zqcl command to start zq calibration. 11. wait for both tdllk and tzqinit completed. 12. the ddr3 sdram is now ready for normal operation.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 73 max. (10 ns; 5tck) 10ns tis tis tis 200 s 500 s notes: 1. from time point "td" until "tk", nop or desl commands must be applied between mrs and zqcal commands. 2. txpr = max. (txs; 5tck) : vih or vil ck, /ck vdd, vddq /reset cke command ba odt dram_rtt mrs * 1 mrs mrs mrs zqcal mr2 mr3 mr1 mr0 ta tb tc td te tf tg th ti tj tk txpr tmrd tzqinit tdllk tmrd tmrd tmod * 2 tcksrx reset and initialization sequence at power-on ramping reset and initialization with stable power the following sequence is required for /reset at no power interruption initialization. 1. assert /reset below 0.2 vdd anytime when reset is needed (all other inputs may be undefined). /reset needs to be maintained for minimum 100ns. cke is pulled low before /reset being de-asserted (minimum time 10ns). 2. follow power-up initialization sequence steps 2 to 12. 3. the reset sequence is now completed; ddr3 sdram is ready for normal operation. max. (10 ns; 5tck) 10ns tis tis tis 100ns 500 s notes: 1. from time point "td" until"tk", nop or desl commands must be applied between mrs and zqcl commands. 2. txpr = max. (txs; 5tck) : vih or vil ck, /ck vdd, vddq /reset cke command ba odt dram_rtt mrs * 1 mrs mrs mrs zqcl mr2 mr3 mr1 mr0 ta tb tc td te tf tg th ti tj tk txpr tmrd tzqinit tdllk tmrd tmrd tmod * 2 tcksrx reset procedure at power stable condition
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 74 programming the mode register for application flexibility, various func tions, features and modes are programmabl e in four mode registers, provided by the ddr3 sdram, as user defined variables, and they must be programmed via a mode register set (mrs) command. as the default values of the mode registers (mr#) are not defined, content of mode registers must be fully initialized and/or re-initial ized, i.e. written, after power-up and/or rese t for proper operation. also the contents of the mode registers can be altered by re-executing the mrs command during normal operation. when programming the mode registers, even if the user chooses to modify only a sub-set of the mrs fields, all address fields within the accessed mode register must be redefined when the mrs command is issued. mrs command and dll reset does not affect array contents, which means these commands can be executed any time after power-up without affecting the array contents. the mode register set command cycle time, tmrd is required to complete the write operation to the mode register and is the minimum time required between two mrs commands. the mrs command to non-mrs command delay, tmod, is required for the dram to update the features exc ept dll reset and is the minimum time required from an mrs command to a non-mrs command excluding nop and desl. the mode register contents can be changed using the same command and timing requirements during normal operation as long as the dra m is in idle state, i.e. all banks are in the precharged state with trp satisfied, all data bursts are comp leted and cke is already high prior to writing into the mode register. the mode registers are divided into various fields depending on the functionality and/or modes. mode register set command cycle time (tmrd) tmrd is the minimum time required from an mrs comm and to the next mrs command. as dll enable and dll reset are both mrs commands, tmrd is applicable between mrs to mr1 for dll enable and mrs to mr0 for dll reset, and not tmod. command mrs nop mrs nop tmrd ck /ck tmrd timing mrs command to non-mrs command delay (tmod) tmod is the minimum time required from an mrs command to a non-mrs command excluding nop and desl. note that additional restrictions may apply, for ex ample, mrs to mr0 for dll reset followed by read. command mrs nop non-mrs nop old setting tmod updating new setting ck /ck tmod timing
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 75 ddr3 sdram mode register 0 [mr0] the mode register mr0 stores t he data for controlling various oper ating modes of ddr3 sdram. it controls burst length, read burst ty pe, /cas latency, test mode, dll re set, wr and dll control for precharge power-down, which include various vendor specific options to make ddr3 sdram useful for various applications. the mode register is written by asserting low on /cs, /r as, /cas, /we, ba0 and ba1, while controlling the states of address pins according to the table below. notes: 1. ba2 and a13 are reserved for future use and must be programmed to 0 during mrs. 2. wr (min.) (write recovery for autoprecharge) is determined by tck (max.) and wr (max.) is determined by tck (mi n.). wr in clock cycles is calculated by dividing twr (in ns) by tck (in ns) and rounding up to the next integer (wr (min.) [cycles] = roundup twr (ns) / tck (ns)). (the wr value in the mode register must be programmed to be equal or larger than wr (min.) this is also used with trp to determine tdal. 0 ppd ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 ba1 0 * 1 ba2 0 * 1 a13 wr a8 0 1 dll reset no yes dll tm /cas latency rbt cl bl mode register 0 a7 0 1 mode normal test a6 0 0 0 0 1 1 1 1 /cas latency a5 0 0 1 1 0 0 1 1 a4 0 1 0 1 0 1 0 1 latency reserved 5 6 7 8 9 10 reserved a2 0 0 0 0 0 0 0 0 a3 0 1 read burst type nibble sequential interleave a12 0 1 dll control for precharge pd slow exit (dll off) fast exit (dll on) burst length a11 0 0 0 0 1 1 1 1 write recovery for autoprecharge a10 0 0 1 1 0 0 1 1 a9 0 1 0 1 0 1 0 1 wr reserved 5 * 2 6 * 2 7 * 2 8 * 2 10 * 2 12 * 2 reserved ba1 0 0 1 1 mrs mode mr0 mr1 mr2 mr3 ba0 0 1 0 1 a1 0 0 1 1 bl 8 (fixed) 4 or 8 (on the fly) 4 (fixed) reserved a0 0 1 0 1 mr0 programming
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 76 ddr3 sdram mode register 1 [mr1] the mode register mr1 stores the dat a for enabling or disabling the dll, output driver st rength, rtt_nom impedance, additive latency, write leveling enable, tdqs enab le and qoff. the mode register 1 is written by asserting low on /cs, /ras, /cas, /we, high on ba0 and lo w on ba1, while controlling the states of address pins according to the table below

!" # $ % &' &'" (&'" )' * + + , --. / $0 1 $ )'( )'(+
'(2 $$/ 3 , 4 $$ ! !5 67 * / 1 !5 7* $$ --. $$/8 4 9$ ! !5 67 * / 1 !5 7* $0 --. )'( )'(+ )'(2 $$/

:

6
2
3
+

$

9$ . &,;
9 . . &,; &99 !
-&'" $ & $ <$
&99 $ <$ & $
2
:
--.= 3 #&- & $ )'(+ )'( )'(2 )'( + )'( +

3 # > >$ )'(2 )'(6 )'(- & )'(- & -&'" '
' # $ # $
6 4 $$ $ & $ <$
+
9>0
9 $ ;9% ;9%
mr1 programming
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 77 ddr3 sdram mode register 2 [mr2] the mode register mr2 stores the data for controlling refresh related features, rtt_wr impedance and /cas write latency (cwl). the mode register 2 is written by asserting low on /cs, /r as, /cas, /we, high on ba1 and low on ba0, while con-trolling the states of addre ss pins according to the table below.

!" # $ $ %& % '( %& )* + ,%))
*& # # - .%* /%& + %,, *& 0 .& 0-& !) %+# 1& 0 .&$ 12&%)/ 31 & %.%%+# # 3,&% & 11 1" 4 5%% %2 6-7 &%+$ %% /% & %% - %%2 +2& - ,/ % %& 0 + 6- &# 1%% &2 0 + )%&%& 8' /&& % ) %& & 6- /))%& *#

'* 9% " %&:
%&: ;*%" %&:
%& %&: < " %&:
< " %&: %&: 9% " %&: %&: ;*%" %&: %& %&: < " %&:

5 ="
> ?
$
$

$
7 5 ="
> ?
$
7 5 ="
> ?
7 5 ="
> ?

$
$
$
$
$ 7 5 ="
> ?
$
$
$ 7 5 ="
> ?
$ 7 5 ="
> ? 7 %% %%2 6- - %%2
6- %& !)% 6- 8@& ),* 6- 53,&%7
* 6- )- %&*% &/ 57 &%+ 53,&%7

0 %&/2 5 7 5a #&7 5#& b a # &7 5 # & b a #&7 5 #& b a #&7 . . . .

12&%)/ 31 50 & %/ .%*7 c;< c;< . mr2 programming
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 78 ddr3 sdram mode register 3 [mr3] the mode register mr3 controls multi purpose registers (mpr). the mode register 3 is written by asserting low on /cs, /ras, /cas, /we, high on ba1 and ba0, while contro lling the states of address pi ns according to the table below. mode register 3 0* 1 1 1 address field a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1 ba2 ba0 a12 mpr mpr loc a13 n otes : 1. ba2, a3 to a13 are reserved for future use (rfu) and must be programmed to 0 during mrs. 2. the predefined pattern will be used for read synchronization. 3 . when mpr control is set for normal operation, mr3 a[2]=0, mr3 a[1:0] will be ignored. a2 0 1 mpr normal operation * 3 data flow from mpr a1 0 0 1 1 mpr location predefined pattern * 2 rfu rfu rfu a0 0 1 0 1 mpr address mpr operation 0* 1 mr3 programming
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 79 burst length (mr0) read and write accesses to the ddr3 are burst oriented, with the burst length being programmable, as shown in the figure mr0 programming. the burst length determines t he maximum number of column locations that can be accessed for a given read or write command. burst length opt ions include fixed bc4, fixed bl8, and on the fly which allows bc4 or bl8 to be selected coincident with the registration of a read on wr ite command via a12 (/bc). reserved states should not be used, as unknown operation or incompatibility with future versions may result. burst chop in case of burst length being fixed to 4 by mr0 setting, the in ternal write operation starts two clock cycles earlier than for the bl8 mode. this means that the starting point for tw r and twtr will be pulled in by two clocks. in case of burst length being selected on the fly via a12(/bc), the inter nal write operation starts at the same point in time like a burst of 8 write operation. th is means that during on-the-fl y control, the starting point for twr and twtr will not be pulled in by two clocks. burst type (mr0) [burst length and sequence] burst length operation starting address (a2, a1, a0) sequential addressing (decimal) interleave addressing (decimal) 4 (burst chop) read 000 0, 1, 2, 3, t, t, t, t 0, 1, 2, 3, t, t, t, t 001 1, 2, 3, 0, t, t, t, t 1, 0, 3, 2, t, t, t, t 010 2, 3, 0, 1, t, t, t, t 2, 3, 0, 1, t, t, t, t 011 3, 0, 1, 2, t, t, t, t 3, 2, 1, 0, t, t, t, t 100 4, 5, 6, 7, t, t, t, t 4, 5, 6, 7, t, t, t, t 101 5, 6, 7, 4, t, t, t, t 5, 4, 7, 6, t, t, t, t 110 6, 7, 4, 5, t, t, t, t 6, 7, 4, 5, t, t, t, t 111 7, 4, 5, 6, t, t, t, t 7, 6, 5, 4, t, t, t, t write 0vv 0, 1, 2, 3, x, x, x, x 0, 1, 2, 3, x, x, x, x 1vv 4, 5, 6, 7, x, x, x, x 4, 5, 6, 7, x, x, x, x 8 read 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 write vvv 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 remark: t: output driver for dat a and strobes are in high impedance. v: a valid logic level (0 or 1), but res pective buffer input ignores level on input pins. x: don?t care. notes: 1. page length is a function of i/o organization and column addressing 2. 0...7 bit number is value of ca [2:0] that c auses this bit to be the first read during a burst.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 80 dll enable (mr1) the dll must be enabled for normal operation. dll ena ble is required during power-up initialization, and upon returning to normal operation after having the dll disabled. the dll is automatically disabled when entering self- refresh operation and is automatically re-enabled upon exit of self-refresh oper ation. any time the dll is enabled and subsequently reset, tdllk clock cycles must occur before a read or synchronous odt command can be issued to allow time for the internal clock to be synchronized with t he external clock. failing to wait for synchronization to occur may result in a violation of the tdqsck, taon or taof parameters. during tdllk, cke must continuously be registered high. ddr3 sdram does not require dll for any write operation. ddr3 does not require dll to be locked prior to any write operation. ddr3 requires dll to be locked only fo r read operation and to achieve synchronous odt timing. dll-off mode ddr3 dll-off mode is entered by setting mr1 bit a0 to 1; th is will disable the dll for subsequent operations until a0 bit set back to 0. the mr1 a0 bit for dll control can be switched either during initialization or later. the dll-off mode operations listed below are an optional feature for ddr3. the maximum clock frequency for dll- off mode is specified by the param eter tckdll_off. there is no mini mum frequency limit besides the need to satisfy the refresh interval, trefi. due to latency counter and timing restrictions, only one value of /cas latency (cl) in mr0 and cas write latency (cwl) in mr2 are supported. the dll-off mode is only required to support setting of both cl = 6 and cwl = 6. dll-off mode will affect the read data clock to data strobe relationship (tdqsck) but not the data strobe to data relationship (tdqsq, tqh, tqhs). special attention is needed to line up read data to controller time domain. comparing with dll-on mode, where tdqsck starts from the rising clock edge (al + cl) cycles after the read command, the dll-off mode tdqsck starts (al + cl ? 1) cycles after the read command. another difference is that tdqsck may not be small compared to tck (it might even be larger than tck) and the difference between tdqsck (min.). and tdqsck (max.) is significantly larger than in dll-on mode. the timing relations on dll-off mode read operation ar e shown at following timing diagram (cl = 6, bl8): ck, /ck command ba dqsdiff_dll-on dq_dll-on dqsdiff_dll-off dq_dll-off dqsdiff_dll-off dq_dll-off read a ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 rl = al + cl = 6 (cl = 6, al = 0) rl (dll-off) = al + (cl - 1) = 5 tdqsck(dll-off)_min tdqsck(dll-off)_max cl = 6 ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 ca1 ca2 ca3 ca4 ca5 ca6 ca7 ca0 dll-off mode read timing operation
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 81 dll on/off switching procedure ddr3 dll-off mode is entered by setting mr1 bit a0 to ?1?; this will disable the dll for subsequent operations until a0 bit set back to ?0?. dll ?on? to dll ?off? procedure to switch from dll ?on? to dll ?off? requires the frequency to be changed during self-refresh outlined in the following procedure: 1. starting from idle state (all ban ks pre-charged, all timings fulfilled, a nd drams on-die termination resistors, rtt, must be in high impedance state before mrs to mr1 to disable the dll.) 2. set mr1 bit a0 to ?1? to disable the dll. 3. wait tmod. 4. enter self-refresh mode; wa it until (tcksre) satisfied. 5. change frequency, in guidance with input clock frequency change during precharge power-down section. 6. wait until a stable clock is available for at least (t cksrx) at dram inputs. afte r stable clock, wait tcksrx before issuing srx command. 7. starting with the self-refresh exit co mmand, cke must continuously be registered high until all tmod timings from any mrs command are satisfied. in addition, if any odt features were enabled in the mode registers when self- refresh mode was entered, the odt signal must continuously be registered lo w until all tmod timings from any mrs command are satisfied. if both odt features were disabled in the mode registers when self-refresh mode was entered, odt signal can be registered low or high. 8. wait txs, then set mode registers with appropriate values (especially an update of cl, cwl and wr may be necessary. a zqcl command may also be issued after txs). 9. wait for tmod, then dram is ready for next command. ta tb tc tc+1 tc+2 te td tf tf+2 tf+1 tg tg+1 th ck command cke odt /ck mrs sre nop srx mrs valid change frequency tckesr tmod tcksre tcksrx txs tmod dll switch sequence from dll-on to dll-off
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 82 dll ?off? to dll ?on? procedure to switch from dll ?off? to dll ?on? (with required frequency change) during self-refresh: 1. starting from idle state (all banks pre-charged, all timi ngs fulfilled and drams on-die termination resistors (rtt) must be in high impedance state bef ore self-refresh mode is entered.) 2. enter self-refresh mode, wait until tcksre satisfied. 3. change frequency, in guidance with input clock frequency change during precharge power-down section. 4. wait until a stable clock is availabl e for at least (tcksrx) at dram inputs. 5. starting with the self-refresh exit command, cke must continuously be registered high until all tdllk timing from subsequent dll reset command is satisfied. in additi on, if any odt features were enabled in the mode registers when self-refresh mode was entered, the odt si gnal must continuously be re gistered low until tdllk timings from subsequent dll reset command is satisfi ed. if both odt features are disabled in the mode registers when self refresh mode was entered, odt signal can be registered low or high. 6. wait txs, then set mr1 bit a0 to ?0? to enable the dll. 7. wait tmrd, then set mr0 bit a8 to ?1? to start dll reset. 8. wait tmrd, and then set mode regist ers with appropriate values (especially an update of cl, cwl and wr may be necessary. after tmod is satisfied from any pr oceeding mrs command, a zqcl command may also be issued during or after tdllk.) 9. wait for tmod, and then dram is ready for next command (remember to wait tdllk after dll reset before applying command requiring a locked dll!). in addition, wait also for tzqoper in case a zqcl command was issued. ck command cke odt /ck ta tb tc tc+1tc+2 te td tf tf+2 tf+1 tg valid mrs mrs mrs srx nop sre change frequency tckesr odtloff + 1x tck tcksre tcksrx tdllk txs tmrd tmrd dll switch sequence from dll-off to dll-on
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 83 additive latency (mr1) a posted /cas read or write command when issued is held for the time of the additive latency (al) before it is issued inside the device. the read or write posted /cas command may be issued with or without auto precharge. the read latency (rl) is controlled by the sum of al and the /cas latency (cl). the value of al is also added to compute the overall write latency (wl). mrs (1) bits a4 and a3 are used to enable additive latency. mrs1 a4 a3 al* 0 0 0 (posted cas disabled) 0 1 cl ? 1 1 0 cl ? 2 1 1 reserved note: al has a value of cl ? 1 or cl ? 2 as per the cl value programmed in the /cas latency mrs setting.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 84 write leveling (mr1) for better signal integrity, ddr3 memory module adopts fly by topology for the commands, addresses, control signals and clocks. the fly by topology has benefits fo r reducing number of stubs a nd their length but in other aspect, causes flight time skew between clock and strobe at every dram on dimm. it makes controller hard to maintain tdqss, tdss and tdsh specificat ion. therefore, the c ontroller should support ?write leveling? in ddr3 sdram to compensate the skew. write leveling is a scheme to adjust dqs to ck relationship by the controller, with a simple feedback provided by the dram. the memory controller involved in the leveling mu st have adjustable delay setting on dqs to align the rising edge of dqs with that of the clock at the dram pin. dram asynchronously feeds back ck, sampled with the rising edge of dqs, through the dq bus. the c ontroller repeatedly delays dqs until a transition from 0 to 1 is detected. the dqs delay established through this exercise would ensure tdqss, tdss and tdsh specification. a conceptual timing of this scheme is shown as below. diff_clock source destination push dqs to capture 0-1 transition diff_dqs diff_clock diff_dqs dq dq x0 0 x1 1 write leveling concept dqs, /dqs driven by the controller during leveling mode must be terminated by the dram, based on the ranks populated. similarly, the dq bus driven by t he dram must also be terminated at the controller. one or more data bits should carry the leveling fee dback to the controller acro ss the dram configurations, 8 and 16. on a 16 device, both byte lanes should be leveled independe ntly. therefore, a separate feedback mechanism should be available for each byte lane. the upper data bi ts should provide the feedb ack of the upper diff_dqs (diff_dqsu) to clock rela tionship whereas the lower data bits would i ndicate the lower diff_dq s (diff_dqsl) to clock relationship. dram setting for write leveling and dram termination function in that mode dram enters into write leveling mode if a7 in mr1 set 1. and after finishing leveling, dram exits from write leveling mode if a7 in mr1 set 0 (mr1 setting involved in the leveling procedure table). note that in write leveling mode, on ly dqs/dqs terminations are activated and deactivated via odt pin, not like normal operation (refer to the dram termination function in the leveling mode table) [mr1 setting involved in the leveling procedure] function mr1 bit e nable disable note write leveling enable a7 1 0 output buffer mode (qoff) a12 0 1 1 note: 1. output buffer mode definition is consistent with ddr2 [dram termination function in the leveling mode] odt pin@dram dqs, /dqs termination dqs termination de-asserted off off asserted on off note: in write leveling mode with its output buffer disabl ed (mr1 [bit7] = 1 with mr1 [bit12] = 1) all rtt_nom settings are allowed; in write leveling mode with its output buffer enabled (mr1 [bit7] = 1 with mr1 [bit12] = 0) only rtt_nom settings of rzq/2, rzq/4 and rzq/6 are allowed.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 85 write leveling procedure memory controller initiates leveling mode of all drams by se tting bit 7 of mr1 to 1. since the controller levelizes rank at a time, the output of other rank must be disabled by setting mr 1 bit a12 to 1. controller may assert odt after tmod, time at which dram is ready to accept the odt signal. controller may drive dqs low and /dqs high after a del ay of twldqsen, at which time dram has applied on-die termination on these signals. after twlmrd, controller pr ovides a single dqs, /dqs edge which is used by the dram to sample ck driven from controller. twlmrd timing is controller dependent. dram samples ck status with rising ed ge of dqs and provides feedback on all the dq bits asynchronously after twlo timing. there is a dq output unce rtainty of twloe defined to allow mism atch on dq bits; there are no read strobes (dqs, /dqs) needed for these dqs. controller samples incoming dq and decides to increment or decrement dqs delay setting and launches the next dqs, /dqs pulse after some time, which is controller dependent. once a 0 to 1 transition is detected, the controller locks dqs delay setting and write le veling is achieved for the device. the below figure describes detailed timing diagr am for overall procedure and the timing parameters are shown in below figure. /ck ck command odt diff_dqs* 4 all dqs, prime dq* 1 remaining dqs notes:1. dram has the option to drive leveling feedback on a prime dq or all dqs. if feedback is driven only on one dq, the remaining dqs must be driven low as shown in above figure, and maintained at this state through out the leveling procedure. 2. mrs : load mr1 to enter write leveling mode. 3. nop : nop or deselec 4. diff_dqs is the differential data strobe (dqs, /dqs). timing reference points are the zero crossing. dqs is shown with solid line, /dqs is shown with dotted line. 5. ck, /ck : ck is shown with solid dark line, where as /ck is drawn with dotted line. 6. dqs needs to fulfill minimum pulse width requirements tdqsh (min.) and tdqsl (min.) as defined for regular writes; the max pulse width is system dependent. tmod t1 t2 twlo twlh twls twlmrd twlo twloe tdqsl (min.) tdqsh (min.) tdqsl (min.) tdqsh (min.) twldqsen mrs * 2 nop * 4 nop nop nop nop nop nop nop nop nop nop * 3 twlh twls * 5 * 2 * 3 * 6 * 6 timing details write leveling sequence
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 86 write leveling mode exit the following sequence describes how th e write leveling mode should be exited: 1. after the last rising strobe edge(se e t111), stop driving the strobe signals (see ~t128). note: from now on, dq pins are in undefined driving mode, and will remain un defined, until tmod after the respective mr command (t145). 2. drive odt pin low (tis must be satisfied) and continue registering low (see t128). 3. after the rtt is switched off: disable write level mode via mr command (see t132). 4. after tmod is satisfied (t145), any valid commands may be registered. (mr commands may already be issued after tmrd (t136). ck, /ck rtt_dqs-/dqs rtt_dq odt dqs-/dqs dq t111 t112 t116 t117 t128 t131 t132 t136 t145 todtl_off tmrd tmod tis twlo + twloe command ba wl_off mrs 1 result = 1 valid valid valid valid timing details write leveling exit
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 87 tdqs, /tdqs function (mr1) tdqs (termination data st robe) is a feature of 8 ddr3 sdram that provides ad ditional termination resistance outputs that may be useful in some system configurations. tdqs is not supported in 16 configurations. when enabled via the mode register, the same termination resistance function is applied to the tdqs and /tdqs pins that are applied to the dqs and /dqs pins. in contrast to the rdqs function of ddr2 sdram, tdqs provides the te rmination resistance function only. the data strobe function of rdqs is not provided by tdqs. the tdqs and dm functions share the sa me pin. when the tdqs function is en abled via the mode register, the dm function is not supported. when the tdqs function is disabled, the dm function is provided and the /tdqs pin is not used. see table tdqs, /t dqs function for details. the tdqs function is available in 8 ddr3 sdram only and must be disabled via the mode register a11 = 0 in mr1 for 16 configurations. [tdqs, /tdqs function] a11@mr1 tdqs enable 0 disable 1 enable notes: 1. if tdqs is enabled, the dm function is disabled. 2. when not used, tdqs function can be disabled to save termination power 3. tdqs function is only available for 8 dram and must be disabled for 16 [function matrix] a11@mr1 (tdqs enable) dm/tdqs nu/ /tdqs 0 dm high-z 1 tdqs /tdqs
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 88 extended temperature usage (mr2) [mode register description] field bits description description asr a6 0 manual sr reference (srt) 1 asr enable (optional) auto self-refresh (asr) (optional) when enabled, ddr3 sdram automatically provides self-refresh power management functions for all supported operating temperature values. if not enabled, the srt bit must be programmed to indicate tc during subsequent self-refresh operation srt a7 0 normal operating temperature range 1 extended (optional) operating temperature range self-refresh temperature (srt) range if asr = 0, the srt bit must be programmed to indicate tc during subsequent self-refresh operation if asr = 1, srt bit must be set to 0 partial array self-refresh (pasr) optional in ddr3 sdram: users should refer to the dr am supplier data sheet and/or the dimm spd to determine if ddr3 sdram devices support the followi ng options or requirements referred to in this material. if pasr (partial array self-refresh) is enabled, data located in areas of the array beyond the specified address range shown in figure of mr2 programming will be lost if self-refresh is entered. data integrity will be maintained if trefi conditions are met and no self-refresh command is issued. /cas write latency (cwl) the /cas write latency is defined by mr2 bits [a3, a5 ], as shown in figure of mr2 programming. /cas write latency is the delay, in clock cycles, between the internal wr ite command and the availability of the first bit of input data. ddr3 sdram does not support any half-clock latencies. the overall write latency (wl) is defined as additive latency (al) + /cas write latency (cwl); wl = al + cwl. for more information on the sup-ported cwl and al settings based on the operating clock frequency, refer to ?standard speed bins?. for detailed write operation refer to ?write operation?. auto self-refresh mode - asr mode (optional) ddr3 sdram provides an auto self-refresh mode (asr) for application ease. asr mode is enabled by setting mr2 bit a6 = 1 and mr2 bit a7 = 0. the dram will manag e self-refresh entry in either the normal or extended (optional) temperature ranges. in th is mode, the dram will also manage se lf-refresh power consumption when the dram operating temperature changes, lower at low te mperatures and higher at high temperatures. if the asr option is not supported by the dram, mr2 bit a6 must be set to 0. if the asr mode is not enabled (mr2 bit a6 = 0), the sr t bit (mr2 a7) must be manually programmed with the operating temperature range required during self-refresh operation. support of the asr option does not automatically imply support of the extended temperature range. self- refresh temperature range - srt (optional) if asr = 0, the self-refresh temperature (srt) range bi t must be programmed to guarantee proper self-refresh operation. if srt = 0, then the dram will set an appropriate refresh rate for self-refresh operation in the normal temperature range. if srt = 1 then the dram will set an a ppropriate, potentially different, refresh rate to allow self-refresh operation in either the normal or extended te mperature ranges. the value of the srt bit can effect self-refresh power consumption, please refer to the idd table for details. for parts that do not support the exte nded temperature range, mr2 bit a7 must be set to 0 and the dram should not be operated outside the normal temperature range.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 89 [self-refresh mode summary] mr2 a6 a7 self-refresh operation allowed operating temperature range for self-refresh mode 0 0 self-refresh rate appropriate for the normal temperature range normal (0 c to +85 c) 0 1 self-refresh rate appropriate for either the normal or extended temperature ranges. the dram must support extended temperature range. the value of the srt bit can effect self- refresh power consumption, pleas e refer to the self- refresh current for details. normal and extended (0 c to +95 c) 1 0 asr enabled (for devices supporting asr and normal temperature range). self-refresh power consumption is temperature dependent normal (0 c to +85 c) 1 0 asr enabled (for devices supporting asr and extended temperature range). self-refresh power consumption is temperature dependent normal and extended (0 c to +95 c) 1 1 illegal dynamic odt (rtt_wr) ddr3 sdram introduces a new feature ?dynamic odt?. in ce rtain application cases and to further enhance signal integrity on the data bus, it is desir able that the termination strength of the ddr3 sdram can be changed without issuing an mrs command. mr2 register locations a9 and a10 configure the dynamic odt settings. in write leveling mode, only rtt_nom is available. for details on dynamic odt operation, refer to ?dynamic odt?.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 90 multi purpose register (mr3) the multi purpose register (mpr) function is used to re ad out predefined system timing calibration bit sequence.

!

" !
#$ #$ ! !
$%" $" $%&" '$%&

(
conceptual block diagram of multi purpose register to enable the mpr, a mode register set (mrs) command must be issued to mr3 register with bit a2 = 1. prior to issuing the mrs command, all banks must be in the idle state (all banks precharged and trp/trpa met). once the mpr is enabled, any subsequent read or reada commands will be redirected to the multi purpose register. the resulting operation when a read or reada command is iss ued is defined by mr3 bits [a1: a0] when the mpr is enabled. when the mpr is enabled, only read or reada commands are allowed until a subsequent mrs command is issued with the mpr disabled (mr3 bit a2=0 ). power-down mode, self -refresh, and any other non- read/reada command are not allowed during mpr enable mode. the /reset function is supported during mpr enable mode. [functional description of mr3 bits for mpr] mr3 a2 a [1:0] mpr mpr-loc function notes 0 don?t care (0 or 1) normal operation, no mpr transaction. all subsequent reads will come from dram array. all subsequent writes will go to dram array. 1 mr3 a [1:0] enable mpr mode, subsequent read/reada commands defined by mr3 a [1:0] bits. 1 note: 1. see available data locations and burst order bit mapping for multi purpose register table
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 91 one bit wide logical interface via all dq pins during read operation ? register read on 8: dq [0] drives information from mpr. dq [7:1] either drive the same informa tion as dq [0], or they drive 0. ? register read on 16: dql [0] and dqu [0] drive information from mpr. dql [7:1] and dqu [7:1] either drive the same information as dql [0], or they drive 0. note: a standardization of which dq is used by ddr3 sdram for mpr reads is strongly recommended to ensure functionality also for amb2 on ddr3 fb-dimm. ? addressing during multi purpose register reads for all mpr agents: ? ba [2:0]: don?t care. ? a [1:0]: a [1:0] must be equal to ?00?b. data read burst order in nibble is fixed ? a [2]: for bl8, a [2] must be equal to 0. burst order is fixed to [0,1,2,3 ,4,5,6,7] * 1 for burst chop 4 cases, the burst order is switched on nibble base a [2] = 0, burst order: 0,1,2,3 * 1 a [2] = 1, burst order: 4,5,6,7 * 1 ? a [9:3]: don?t care ? a10(ap): don?t care ? a12(/bc): selects burst chop mode on-the-fly, if enabled within mr0 ? a11: don?t care ? regular interface functionality during register reads: ? support two burst ordering which are switched with a2 and a [1:0] = 00. ? support of read burst chop (mrs and on-the-fly via a12(/bc). ? all other address bits (remaining column address bits including a10, all bank address bits) will be ignored by the ddr3 sdram. ? regular read latencies and ac timings apply. ? dll must be locked prior to mpr reads. note: burst order bit 0 is assigned to lsb and burst order bit 7 is assigned to msb of the selected mpr agent.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 92 functional block diagrams figures below provide functional block di agrams for the multi purpose register in 8 and 16 ddr3 sdram. memory array copy to dq[7:0] q mpr 64 read path dq[7:0] bytelane 8 8 8 8 8 dm dqs /dqs functional block diagram of multi purpose register in 8 ddr3 sdram
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 93 memory array copy to dqu[7:0] 64 read path dqu[7:0] bytelaneupper bytelanelower 8 8 8 8 8 8 8 dmu dqsu /dqsu read path dql[7:0] dml dqsl /dqsl copy to dql[7:0] q mpr 64 8 8 8 8 8 functional block diagram of multi purpose register in 16 ddr3 sdram
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 94 register address table the table below provides an overview of the available data locations, how they are addressed by mr3 a [1:0] during a mr0 to mr3, and how their individual bits are mapped in to the burst order bits dur ing a multi purpose register read. [available data locations and burst order bit mapping for multi purpose register] note: 1. burst order bit 0 is assigned to lsb and burst or der bit 7 is assigned to msb of the selected mpr agent. relevant timing parameters the following ac timing parameters are important for opera ting the multi purpose register: trp, tmrd, tmod and tmprr. besides these timings, all other timing parameters need ed for proper operation of the ddr3 sdram need to be observed. [mpr recovery time tmprr] symbol description tmprr multi purpose register recovery time, defi ned between end of mpr read burst and mrs which reloads mpr or disables mpr function mr3 a [2] mr3 a [1:0] function burst length read address a [2:0] burst order and data pattern notes bl8 000 burst order 0,1,2,3,4,5,6,7 pre-defined pattern [0,1,0,1,0,1,0,1] 1 bc4 000 burst order 0,1,2,3, pre-defined pattern [0,1,0,1] 1 1 00 read predefined pattern for system calibration bc4 100 burst order 4,5,6,7 pre-defined pattern [0,1,0,1] 1 bl8 000 burst order 0,1,2,3,4,5,6,7 1 bc4 000 burst order 0,1,2,3 1 1 01 rfu bc4 100 burst order 4,5,6,7 1 bl8 000 burst order 0,1,2,3,4,5,6,7 1 bc4 000 burst order 0,1,2,3 1 1 10 rfu bc4 100 burst order 4,5,6,7 1 bl8 000 burst order 0,1,2,3,4,5,6,7 1 bc4 000 burst order 0,1,2,3, 1 1 11 rfu bc4 100 burst order 4,5,6,7 1
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 95 protocol examples protocol example: read out predetermined read-calibration pattern multiple reads from multi purpose register, in order to do system level read timing calibration based on predetermined and standardized pattern. protocol steps: ? precharge all ? wait until trp is satisfied ? mrs mr3, op-code ?a2 = 1 ? and ?a[1:0] = 00? ? redirect all subsequent reads into the multi pur pose register, and load pre-defined pattern into mpr. ? wait until tmrd and tmod are satisfied (multi purpose re gister is then ready to be read). during the period mr3 a2 =1, no data write operation is allowed. ? read: ? a [1:0] = ?00? (data burst order is fixed starting at nibble, always 00 here) ? a [2] = ?0? (for bl8, burst orde r is fixed as 0, 1,2,3,4,5,6,7) ? a12(/bc) = 1 (use regular burst length of 8) ? all other address pins (including ba [2:0] and a10(ap)): don?t care. ? after rl = al + cl, dram bursts out t he predefined read calibration pattern. ? memory controller repeats these calibration reads until read data capture at memory controller is optimized. ? after end of last mpr read burst wa it until tmprr is satisfied. ? mrs mr3, op-code ?a2 = 0? and ?a[1:0] = valid data but value are don?t care? ? all subsequent read and write accesses will be regular reads and writes from/to the dram array. ? wait until tmrd and tmod are satisfied ? continue with ?regular? dram commands, like activate a memory bank for regular read or write access, 3 3 valid 1 0 0 * 2 00 00 valid 1 0 valid 0 0 valid * 1 0 0 valid 0 0 valid 0 valid 0 * 2 tmod * 1 tmrd rl notes: 1. read with bl8 either by mrs or otf 2. memory control must drive 0 on a[2:0] vih or vil ck command ba a[1:0] a[2] a[9:3] a10(ap) a[11] a12(/bc) a[15:13] dqs, /dqs dq tmprr pall mrs nop nop read nop mrs nop t0 t4 t5 t9 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t39 trp tmod 0 /ck mpr readout of predefined pattern, bl8 fixed burst order, single readout
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 96 tmod * 1 tmrd rl rl notes: 1. read with bl8 either by mrs or otf 2. memory control must drive 0 on a[2:0] vih or vil ck command ba a[1:0] a[2] a[9:3] a10, ap a[11] a12(/bc) a[15:13] dqs, /dqs dq tmprr pall mrs nop nop read mrs nop * 1 read nop nop t0 t4 t5 t9 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t43 trp tccd tmod 3 3 valid valid 00 00 valid valid 0 1 0 valid valid 0 0 valid valid * 1 * 1 0 0 valid valid 0 0 valid valid 0 valid 0 * 2 0 * 2 1 0 0 * 2 0 * 2 /ck mpr readout of predefined pattern, bl8 fixed burst order, back-to-back readout t0 t4 t5 t9 t17 t18 t19 t20 t21 t22 tmod * 1 * 1 * 1 tmrd 3 3 valid 0 valid 0 1 0 0 00 00 valid 0 1 0 valid 0 0 valid 0 0 valid 0 0 valid rl rl notes:1. read with bc4 either by mrs or otf 2. memory control must drive 0 on a[1:0] 3. a[2] = 0 selects lower 4 nibble bits 0 ... 3 4. a[2] = 1 selects upper 4 nibble bits 4 ... 7 ck command ba a[1:0] a[2] a[9:3] a10(ap) a[11] a12(/bc) a[15:13] dqs, /dqs dq tmprr pall mrs nop nop read mrs nop * 1 read nop nop t23 t24 t25 t26 t27 t28 t29 t30 t31 t43 trp tccd tmod * 2 * 3 valid 0 1 valid valid valid valid valid * 2 * 4 vih or vil /ck mpr readout predefined pattern, bc4, lower nibble then upper nibble
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 97 t0 t4 t5 t9 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t43 tmod * 1 * 1 * 1 tmrd 3 3 valid 0 valid 0 1 0 1 00 00 valid 0 1 0 valid 0 0 valid 0 0 valid 0 0 valid rl rl notes:1. read with bc4 either by mrs or otf 2. memory control must drive 0 on a[1:0] 3. a[2] = 0 selects lower 4 nibble bits 0 ... 3 4. a[2] = 1 selects upper 4 nibble bits 4 ... 7 ck, /ck command ba a[1:0] a[2] a[9:3] a10, ap a[11] a12(/bc) a[15:13] dqs, /dqs dq tmprr pall mrs nop nop read mrs nop * 1 read nop nop trp tccd tmod * 2 * 4 valid 0 0 valid valid valid valid valid * 2 * 3 vih or vil mpr readout of predefined pattern, bc4, upper nibble then lower nibble
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 98 operation of the ddr3 sdram read timing definition read timing is shown in the following figure and is applied when the dll is enabled and locked. rising data strobe edge parameters: ? tdqsck min/max describes the allowed range for a rising data strobe edge relative to ck, /ck. ? tdqsck is the actual position of a rising strobe edge relative to ck, /ck. ? tqsh describes the dqs, /dqs differential output high time. ? tdqsq describes the latest valid tr ansition of the associated dq pins. ? tqh describes the earliest invalid tran sition of the associated dq pins. falling data strobe edge parameters: ? tqsl describes the dqs, /dqs differential output low time. ? tdqsq describes the latest valid tr ansition of the associated dq pins. ? tqh describes the earliest invalid tran sition of the associated dq pins. tdqsq; both rising/falling edges of dqs, no tac defined. ck /dqs associated dq pins /ck tdqsck tdqsck tqsl tqsh tqh tdqsq tdqsq tqh tdqsck(max.) tdqsck(min.) tdqsck(min.) tdqsck(max.) dqs rising strobe region rising strobe region read timing definition
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 99 ? ck, /ck crossing to dqs, /dqs crossing ? tdqsck; rising edges only of ck and dqs ? tqsh; rising edges of dqs to falling edges of dqs ? tqsl; rising edges of / dqs to falling edges of /dqs ? tlz (dqs), thz (dqs) for preamble/pos tamble (see thz (dqs), tlz (dqs) notes: within a burst, rising strobe edge is not necessarily fixed to be always at tdqsck(min.) or tdqsck(max.). instead, rising strobe edge can vary between tdqsck(min.) or tdqsck(max.) within a burst. likewise tlz(dqs)(min.) and thz(dqs)(min.) are not tied to tdqsck(min.) (early strobe case) and tlz(dqs)(max.) and thz(dqs)(max.) are not tied to tdqsck(max.) (late strobe case). the minimum pulse width of read preamble is defined by trpre(min.). the minimum pulse width of read preamble is defined by trpst(min.). /ck ck dqs, /dqs early strobe trpre trpst tlz(dqs)(min.) tdqsck(min.) tdqsck(min.) tdqsck(min.) dqs, /dqs late strobe tdqsck(min.) trpre trpst tlz(dqs)(max.) thz(dqs)(max.) bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 rl measured to this point tdqsck(max.) tdqsck(max.) tdqsck(max.) tdqsck(max.) tqsh tqsl tqsh tqsl ddr3 clock to data strobe relationship
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 100 ? dqs, /dqs crossing to data output ? tdqsq; both rising/falling edges of dqs, no tac defined notes: 1. bl8, rl = 5(al = 0, cl = 5). 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 0] and a12 = 1 during read command at t0. 5. output timings are referenced to vddq/2, and dll on for locking. 6. tdqsq defines the skew between dqs, /dqs to data and does not define dqs, /dqs to clock. 7. early data transitions may not always happen at the same dq. data transitions of a dq can vary(either early or late) within a busy. vih or vil read ck /ck t0 t5 t7 t9 t10 t4 t6 t8 command* 3 dqs, /dqs dq* 2 (last data valid) nop address* 4 bank coln dq* 2 (first data no longer valid) all dqs collectively trpst rl = al + cl tqh tqh trpre tdqsq(max.) dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 data valid data valid dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 tlz(dq)(min.) tlz(dq)(max.) thz(dq)(max.) tdqsq(max.) ddr3 data strobe to data relationship
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 101 tlz (dqs), tlz (dq), thz (dqs), thz (dq) notes thz and tlz transitions occur in the same access time as valid data transitions. these parameters are referenced to a specific voltage level whic h specifies when the device output is no lo nger driving thz(dqs) and thz(dq), or begins driving tlz(dqs), tlz(dq). the figure below shows a method to calculate the point when device is no longer driving thz(dqs) and thz(dq), or begins driving tlz(dqs), tlz(dq) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. the parameters tlz(dqs), tlz(dq), thz(dqs), and thz( dq) are defined as singled ended. voh ? x mv voh ? 2x mv vol + 2x mv vol + x mv thz (dqs), thz (dq) thz (dqs), thz (dq) end point = 2 t1 - t2 t1 t2 tlz (dqs), tlz (dq) tlz (dqs), tlz (dq) begin point = 2 t1 - t2 tlz (dqs): ck-/ck rising crossing at rl-1 tlz (dq): ck-/ck rising crossing at rl vtt + 2x mv vtt + x mv vtt ? x mv vtt ? 2x mv t2 t1 thz (dqs), thz (dq) with bl8: ck-/ck rising crossing at rl + 4nck thz (dqs), thz (dq) with bl4: ck-/ck rising crossing at rl + 2nck method for calculating transitions and endpoints
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 102 read operation during read or write command ddr3 will support bc4 and bl8 on the fly using address a12 during the read or write (auto precharge can be enabled or disabled). ? a12 = 0, bc4 (bc4 = burst chop, tccd = 4) ? a12 = 1, bl8 a12 will be used only for burst length control, not a column address. the burst read command is initiated by having /cs and /cas low while holding /ras and /we high at the rising edge of the clock. the address inputs de termine the starting column address fo r the burst. the delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (rl). the data strobe output (dqs) is driven low 1 clock cy cle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchron ized with the rising edge of the data st robe (dqs). each subsequent data-out appears on the dq pin in phase with the dqs signal in a source synchronous manner. the rl is equal to an additive latency (al) plus /cas latency (cl). the cl is defined by the mode register 0 (mr0), similar to the existing sdr and ddr-i sdrams. the al is defined by the mode register 1 read /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 command* 3 dqs, /dqs dq* 2 nop cl = 5 address* 4 bank col n dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 trpre trpst rl = al + cl notes: 1. bl8, al = 0, rl = 5, cl = 5 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read comman d at t0. vih or vil burst read operation, rl = 5
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 103 read /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 command* 3 dqs, /dqs* 2 dq nop al = 4 trpre rl = al + cl dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 cl = 5 trpst bank col n notes: 1. bl8, rl = 9, al = (cl ? 1), cl = 5 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read command at t0. vih or vil address* 4 burst read operation, rl = 9 read read nop /ck ck t0 t4 t3 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 command* 3 dqs, /dqs dq* 2 rl = 5 tccd trpre rl = 5 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 dout n dout n+1 dout b+2 dout b+3 dout b+4 dout b+5 dout b+6 dout b+7 dout b dout b+1 trpst notes: 1. bl8, rl = 5 (cl = 5, al = 0). 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read command at t0 and t4. vih or vil address* 4 nop bank col n bank col b read (bl8) to read (bl8)
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 104 read read nop /ck ck t0 t4 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 command* 3 dqs, /dqs dq* 2 rl = 5 tccd trpre trpre rl = 5 dout n+2 dout n+3 dout n dout n+1 dout b+2 dout b+3 dout b dout b+1 trpst bank col n bank col b notes: 1. bc4, rl = 5 (cl = 5, al = 0). 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [1, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 0 during read command at t0 and t4. vih or vil trpst address* 4 nop read (bc4) to read (bc4) read writ nop /ck ck t0 t4 t3 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 t15 command* 3 dqs, /dqs rl = 5 read to writ command delay = rl + tccd + 2tck ? wl trpre twpre wl = 5 tbl = 4 clocks twr bank col n bank col b notes: 1. bl8, rl = 5 (cl = 5, al = 0), wl = 5 (cwl = 5, al = 0). 2. dout n = data-out from column n, din b= data-in from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read command at t0 and writ command t6. vih or vil address* 4 nop twtr dq* 2 trpst dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 dout n dout n+1 din b+2 din b+3 din b+4 din b+5 din b+6 din b+7 din b+1 din b twpst read (bl8) to write (bl8)
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 105 read writ nop /ck ck t0 t4 t3 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 t15 command* 3 dqs, /dqs rl = 5 read to writ command delay = rl + tccd/2 + 2tck ? wl trpre twpre wl = 5 tbl = 4 clocks bank col n bank col b notes: 1. bc4, rl = 5 (cl = 5, al = 0), wl = 5 (cwl = 5, al = 0). 2. dout n = data-out from column n, din b= data-in from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 0 during read command at t0 and writ command t4. vih or vil address* 4 nop dq* 2 trpst dout n+2 dout n+3 dout n dout n+1 din b+2 din b+3 din b+1 din b twpst twr twtr read (bc4) to write (bc4) otf read read nop /ck ck t0 t4 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 command* 3 dqs, /dqs dq* 2 rl = 5 tccd trpre rl = 5 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 dout n dout n+1 dout b+2 dout b+3 dout b dout b+1 notes: 1. rl = 5 (cl = 5, al = 0). 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 0 during read command at t4. bl8 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read command at t0. vih or vil address* 4 nop bank col n bank col b trpst read (bl8) to read (bc4) otf
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 106 read read nop ck /ck t0 t4 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 command* 3 dqs, /dqs dq* 2 rl = 5 tccd trpre trpre rl = 5 dout n+2 dout n+3 dout n dout n+1 dout b+2 dout b+3 dout b dout b+1 dout b+4 dout b+5 dout b+6 dout b+7 notes: 1. rl = 5 (cl = 5, al = 0). 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 0 during read command at t0. bl8 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read command at t4. vih or vil address* 4 nop trpst trpst bank col n bank col b read (bc4) to read (bl8) otf read writ nop /ck ck t0 t4 t3 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 t15 command* 3 dqs, /dqs rl = 5 trpre twpre wl = 5 tbl = 4 clocks bank col n bank col b notes: 1. rl = 5 (cl = 5, al = 0), wl = 5 (cwl = 5, al = 0). 2. dout n = data-out from column n , din b= data-in from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 0 during read command at t0. bl8 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 1 during writ command at t4. vih or vil address* 4 nop dq* 2 trpst dout n+2 dout n+3 dout n dout n+1 din b+2 din b+3 din b+1 din b din b+6 din b+7 din b+5 din b+4 twpst read to writ command delay = rl + tccd/2 + 2tck ? wl twr twtr read (bc4) to write (bl8) otf
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 107 read writ nop /ck ck t0 t4 t3 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 t15 command* 3 dqs, /dqs rl = 5 read to writ command delay = rl + tccd + 2tck ? wl trpre twpre wl = 5 bank col n bank col b notes: 1. rl = 5 (cl = 5, al = 0), wl = 5 (cwl = 5, al = 0). 2. dout n = data-out from column n, n din b= data-in from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read command at t0. bc4 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 0 during writ command at t6. vih or vil address* 4 nop dq* 2 trpst dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 dout n dout n+1 din b+2 din b+3 din b+1 din b twpst tbl = 4 clocks twr twtr read (bl8) to write (bc4) otf read pre /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 command* 3 dqs, /dqs dq* 2 nop nop cl = 5 address* 4 bank col n dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 trpre trpst rl = al + cl notes: 1. bl8, al = 0, rl = 5, cl = 5 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read comman d at t0. vih or vil trtp = 4 nck trp burst read precharge operation, rl = 5
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 108 read /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 command* 3 dqs, /dqs* 2 dq nop al = 4 trpre rl = al + cl dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 cl = 5 trpst bank col n notes: 1. bl8, rl = 9, al = (cl 1), cl = 5 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read command at t0. vih or vil address* 4 pre nop trtp = 4 nck internal read command starls here trp burst read precharge operation, rl = 9
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 109 write timing definition t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 wl = al + cwl tdqss(min) tdqss(max) twpre (min) t10 tdqss tdsh tdsh tdsh tdsh tdqsh (min) tdqsh tdqsl tdqsh tdqsl tdss tdss tdss tdss tdss nop writ nop nop nop nop nop nop nop nop nop twpst (min) notes: bl8, wl = 5 (al = 0, cwl = 5) 1. din n = data-in from column n. 2. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. bl8 setting activated by mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during writ command at t0. 4. tdqss must be met at each rising clock edge. 5. vih or vil command * 3 dq * 2 dqs, /dqs address* 4 din n din n + 1 din n + 2 din n + 3 din n + 4 din n + 5 din n + 6 din n + 7 bank, col n tdqsh tdqsl tdqsh tdqsl (min) tdqsl twpre (min) tdsh tdsh tdsh tdsh tdqsh (min) tdqsh tdqsl tdqsh tdqsl tdss tdss tdss tdss tdss twpst (min) dq * 2 dqs, /dqs din n din n + 1 din n + 2 din n + 3 din n + 4 din n + 5 din n + 6 din n + 7 tdqsh tdqsl tdqsh tdqsl (min) tdqsl twpre (min) tdqss tdsh tdsh tdsh tdsh tdqsh (min) tdqsh tdqsl tdqsh tdqsl tdss tdss tdss tdss tdss twpst (min) dq * 2 dqs, /dqs din n din n + 1 din n + 2 din n + 3 din n + 4 din n + 5 din n + 6 din n + 7 tdqsh tdqsl tdqsh tdqsl (min) tdqsl 1 ck /ck * write timing definition
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 110 write operation during read or write command ddr3 will support bc4 and bl8 on the fly using address a12 during the read or write (auto precharge can be enabled or disabled). ? a12 = 0, bc4 (bc4 = burst chop, tccd = 4) ? a12 = 1, bl8 a12 will be used only for burst length control, not a column address. the burst write command is initiated by having /cs, /cas and /we low while holding /ras high at the rising edge of the clock. the address inputs determine the starting column address. write latency (wl) is equal to (al + cwl). a data strobe signal (dqs) should be driven low (preamble) one clock prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at the first ri sing edge of the dqs following the preamble. the tdqss specification must be satisfied for wr ite cycles. the subsequent burst bit dat a are issued on successive edges of the dqs until the burst length of 4 is completed. when the burst has finished, any additional data supplied to the dq pins will be ignored. the dq signal is ignored after th e burst write operation is complete. the time from the completion of the burst write to bank prec harge is the write recovery time (twr). writ /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 command* 3 dq* 2 nop twpre wl = al + cwl bank col n notes: 1. bl8, wl = 5 (al = 0, cwl = 5) 2. din n = data-in from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during writ command at t0. vih or vil address* 4 dqs, /dqs twpst din n din n+1 din n+2 din n+3 din n+4 din n+5 din n+6 din n+7 burst write operation, wl = 5
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 111 writ /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 command* 3 dq* 2 nop al = 4 twpre wl = al + cwl cwl = 5 twpst bank col n notes: 1. bl8, wl = 9 (al = (cl ? 1), cl = 5, cwl = 5) 2. din n = data-in from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during writcommand at t0. vih or vil address* 4 din n din n+1 din n+2 din n+3 din n+4 din n+5 din n+6 din n+7 dqs, /dqs burst write operation, wl = 9 writ read /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 tn tn+1 tn+2 command* 3 dq* 2 nop twpre bank col n bank col b vih or vil address* 4 dqs, /dqs din n din n+1 din n+2 din n+3 twtr* 5 twpst wl = 5 rl = 5 notes: 1. bc4, wl = 5, rl = 5. 2. din n = data-in from column n; dout b = data-out from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [1, 0] during writ command at t0 and read command at tn. 5. twtr controls the write to read delay to the same device and starts with the first rising clock edge after the last write data shown at t7. write to read operation
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 112 writ pre /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 tn tn+1 tn+2 command* 3 dq* 2 nop twpre bank col n vih or vil address* 4 dqs, /dqs din n din n+1 din n+2 din n+3 twr* 5 twpst wl = 5 notes: 1. bc4, wl = 5, rl = 5. 2. din n = data-in from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [1, 0] during writ command at t0. 5. the write recovery time (twr) referenced from the first rising clock edge after the last write data shown at t7. twr specifies the last burst write cycle until the precharge command can be issued to the same bank . write to precharge operation writ writ nop /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 command* 3 dq* 2 nop twpre bank col n bank col b vih or vil address* 4 dqs, /dqs din b din b+1 din n+6 din n+7 din b+2 din b+3 din b+4 din b+5 din b+6 din b+7 tccd twpst wl = 5 wl = 5 notes: 1. bl8, wl = 5 (cwl = 5, al = 0) 2. din n (or b) = data-in from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during writ c ommand at t0 and t4. din n+2 din n+3 din n din n+1 din n+4 din n+5 twr twtr tbl = 4 clocks write (bl8) to write (bl8)
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 113 writ writ /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 command* 3 dq* 2 nop nop twpre bank col n bank col b vih or vil address* 4 dqs, /dqs din b din b+1 din b+2 din b+3 tccd twpre twpst twpst wl = 5 wl = 5 notes: 1. bc4, wl = 5 (cwl = 5, al = 0) 2. din n (or b) = data-in from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by either mr0 bit [a1, a0] = [0, 1] and a12 = 0 during writ command at t0 and t4. din n+2 din n+3 din n din n+1 twr twtr tbl = 4 clocks write (bc4) to write (bc4) writ read /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 t14 command* 3 dq* 2 nop nop twpre bank col n bank col b vih or vil address* 4 dqs, /dqs din n+6 din n+7 twpst wl = 5 rl = 5 notes: 1. rl = 5 (cl = 5, al = 0), wl = 5 (cwl = 5, al = 0) 2. din n = data-in from column n; dout b = data-out from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during writ comma nd at t0. read command at t13 can be either bc4 or bl8 depending on mr0 bit [a1, a0] and a12 status at t13. din n+2 din n+3 din n din n+1 din n+4 din n+5 twtr write (bl8) to read (bc4/bl8)
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 114 writ read /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 t14 command* 3 dq* 2 nop nop twpre bank col n bank col b vih or vil address* 4 dqs, /dqs tbl = 4 clocks twpst wl = 5 notes: 1. bc4, rl = 5 (cl = 5, al = 0), wl = 5 (cwl = 5, al = 0) 2. din n = data-in from column n; dout b = data-out from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 0 during writ command at t0. read command at t13 can be either bc4 or bl8 depending on mr0 bit [a1, a0] and a12 status at t13. din n+2 din n+3 din n din n+1 twtr rl = 5 write (bc4) to read (bc4/bl8) writ writ /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 t14 command* 3 dq* 2 nop nop twpre bank col n bank col b vih or vil address* 4 dqs, /dqs din b din b+1 din n+6 din n+7 din b+2 din b+3 tccd twpst wl = 5 notes: 1. wl = 5 (cwl = 5, al = 0) 2. din n (or b) = data-in from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 1 during writ command at t0. bc4 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 0 during writ command at t4. din n+2 din n+3 din n din n+1 din n+4 din n+5 twr twtr tbl = 4 clocks wl = 5 write (bl8) to write (bc4)
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 115 writ writ /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 t14 command* 3 dq* 2 nop nop twpre bank col n bank col b vih or vil address* 4 dqs, /dqs din b din b+1 din b+2 din b+3 din b+4 din b+5 din b+6 din b+7 tccd twpre twpst twpst wl = 5 notes: 1. wl = 5 (cwl = 5, al = 0) 2. din n (or b) = data-in from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 0 during writ command at t0. bl8 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 1 during writ command at t4. din n+2 din n+3 din n din n+1 twr twtr tbl = 4 clocks wl = 5 write (bc4) to write (bl8)
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 116 write timing violations motivation generally, if timing parameters are violated, a complete rese t/initialization procedure has to be initiated to make sure the dram works properly. however it is desirable for certain minor violations, that the dram is guaranteed not to "hang up" and error to be limited to that part icular operation. for the following it will be assumed that there are no timing violations w.r.t to the write command itself (including odt etc.) and that it does satisfy all ti ming requirements not mentioned below. data setup and hold violations should the data to strobe timing requirements (tds, tdh) be violated, for any of the st robe edges associated with a write burst, then wrong data might be written to the me mory location addressed with this write command. in the example (figure write timing parameters) the releva nt strobe edges for write burst a are associated with the clock edges: t5, t5.5, t6, t6.5, t7, t7.5, t8, t8.5. subsequent reads from that location might result in unpredictable read data, however the dram will work properly otherwise. strobe to strobe and strobe to clock violations should the strobe timing requirements (tdqsh, tdqsl, twpre, twpst) or t he strobe to clock timing requirements (tdss, tdsh tdqss) be violated for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with the offendi ng write command. subsequent reads from that location might result in unpredictable read data, however the dram will work properly otherwise. in the example (figure write timing parameters) the releva nt strobe edges for write burst a are associated with the clock edges: t4, t4.5, t5, t5.5, t6, t6.5, t7, t7.5, t8, t8.5 and t9. any timing requirements starting and ending on one of these strobe edges are t8, t8.5, t9, t9.5, t10, t 10.5, t11, t11.5, t12, t 12.5 and t13. some edges are associated with both bursts. writ writ nop /ck ck t0 t4 t3 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 command* 3 dqs, /dqs dq* 2 odtl wl bl/2 + 2 + odtl twpre twpst vih or vil tdqsl tdqsh tdsh address* 4 /cs nop tdss tdqss a b tdh tds write timing parameters
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 117 write data mask one write data mask (dm) pin for each 8 data bits (dq) wi ll be supported on ddr3 sdrams, consistent with the implementation on ddr-i sdrams. it has identical timings on wr ite operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to ensure matched system timing. dm is not used during read cycles. dq dqs /dqs t1 t2 t3 t4 t5 t6 dm write mask latency = 0 in in in in in in in in data mask timing /ck ck dqs, /dqs dq dm dqs, /dqs dq dm command [tdqss(min.)] twr tdqss wl tdqss wl [tdqss(max.)] writ nop in0 in2 in3 in0 in2 in3 data mask function, wl = 5, al = 0 shown
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 118 precharge the precharge command is used to prec harge or close a bank that has been ac tivated. the precharge command is triggered when /cs, /ras and /we are low and /cas is hi gh at the rising edge of the clock. the precharge command can be used to precharge each bank independently or all banks simultaneously. four address bits a10, ba0, ba1 and ba2 are used to define which bank to precharge when the command is issued. [bank selection for precharge by address bits] a10 ba0 ba1 ba2 precharged bank(s) l l l l bank 0 only l h l l bank 1 only l l h l bank 2 only l h h l bank 3 only l l l h bank 4 only l h l h bank 5 only l l h h bank 6 only l h h h bank 7 only h all banks 0 to 7 remark: h: vih, l: vil, : vih or vil
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 119 auto precharge operation before a new row in an active bank can be opened, the ac tive bank must be precharged using either the precharge command or the auto precharge function. when a read or a write command is given to the ddr3 sdram, the /cas timing accepts one extra address, column address a10, to a llow the active bank to automat ically begin precharge at the earliest possible moment during the bu rst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is execut ed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write command is issued, then the auto precharge function is engaged. during auto precharge, a read command will execut e as normal with the exception that the active bank will begin to precharge on the rising edge which is /cas late ncy (cl) clock cycles before the end of the read burst. auto precharge can also be implemented during write commands. the precharge operation engaged by the auto precharge command will not begin until the la st data of the burst wr ite sequence is properly stored in the memory array. this feature allows the prec harge operation to be partially or completely hidden during burst read cycles (dependent upon /cas latency) thus improving system performance for random data access. the /ras lockout circuit internally delays the precharge operation until the array restore ope ration has been completed so that the auto precharge command may be issued with any read or write command. burst read with auto precharge if a10 is high when a read command is issued, the read with auto precharge function is engaged. the ddr3 sdram starts an auto precharge operati on on the rising edge which is (al + bl/2) cycles later from the read with ap command when tras (min.) is satisfied. if tras (min.) is not satisfied at the ed ge, the start point of auto precharge operation will be delayed until tras (min.) is sati sfied. a new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) the /ras precharge time (trp) has been satisfied from the clock at which the auto precharge begins. (2) the /ras cycle time (trc) from the prev ious bank activation has been satisfied. burst write with auto precharge if a10 is high when a write command is issued, the writ e with auto precharge function is engaged. the ddr3 sdram automatically begins precharge operation after the co mpletion of the burst writes plus write recovery time (twr). the bank-undergoing auto precha rge from the completion of the writ e burst may be reactivated if the following two conditions are satisfied. (1) the data-in to bank activate delay time (twr + trp) has been satisfied. (2) the /ras cycle time (trc) from the prev ious bank activation has been satisfied.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 120 auto-refresh the refresh command (ref) is used during normal opera tion of the ddr3 sdrams. this command is non persistent, so it must be issued each time a refresh is required. the ddr3 sdram requires refresh cycles at an average periodic interval of trefi. when /cs, /ras and /cas are held low and /we high at the rising edge of the clock, the chip enters a refresh cycle. all banks of t he sdram must be precharged and idle for a minimum of the precharge time trp(min) before the refresh command can be applied. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during a refresh command. an internal address counter supplies the addresses during the refresh cycle. no control of the ex ternal address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharged (idle) state. a delay between the refresh command and the nex t valid command, except nop or desl, must be greater than or equal to the minimum refresh cycle time trfc(min) as shown in the following figure. note that the trfc timing parameter depends on memory density. in general, a refresh command needs to be issued to the ddr3 sdram regularly every trefi interval. to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of 8 refresh commands can be postponed during operation of the ddr3 sdram, meaning that at no point in time more than a to tal of 8 refresh commands are allowed to be postponed. in case that 8 refresh commands are postponed in a row, the resulting maximu m interval between the surrounding refresh commands is limited to 9 trefi. a maximum of 8 additional refresh co mmands can be issued in advance (?pulled in?), with each one reducing the number of regular refresh commands requir ed later by one. note that pulling in more than 8 refresh commands in advance does not further reduce the number of regular refresh commands required later, so that the resulting maximum interval between two surrounding refresh commands is limited to 9 trefi. at any given time, a maximum of 16 ref commands can be issued within trefi. before entering self-refresh mode, all postponed refresh commands must be executed. nop pre ck /ck t0 t1 t2 t3 cke command trp vih trfc trfc ref ref nop any command refresh command timing trefi trfc t 9 trer 8 ref-commands postponed postponing refresh command trefi trfc t 9 trer 8 ref-commands postponed pulling-in refresh command
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 121 self-refresh the self-refresh command can be used to retain data in the ddr3 sdram, even if the rest of the system is powered down. when in the self-refresh mode, the ddr3 sdram re tains data without external clocking. the ddr3 sdram device has a built-in timer to accommodate self-refresh oper ation. the self-refresh entry (self) command is defined by having /cs, /ras, /cas and cke held low wi th /we high at the rising edge of the clock. before issuing the self-refresh entry command, the ddr3 s dram must be idle with all bank precharge state with trp satisfied. also, on-die termination must be turned o ff before issuing self-refresh entry command, by either registering odt pin low ?odtl + 0.5tck ? prior to the self-refresh entry command or using mrs to mr1 command. once the self-refresh entry command is registered, cke mu st be held low to keep the device in self-refresh mode. the dll is automatically disabled upon entering self-refresh and is automatically enabled (including a dll-reset) upon exiting self-refresh. when the ddr3 sdram has entered self-re fresh mode all of the external cont rol signals, except cke and /reset, are ?don?t care?. for proper self-refr esh operation, all power supply and reference pins (vdd, vddq, vss, vssq, vrefca and vrefdq) must be at valid levels. the dram initiates a minimum of one refresh command internally within tckesr period once it enters self-refresh mode. the clock is internally disabled during self-refresh operat ion to save power. the minimum time that the ddr3 sdram must remain in self-refresh mode is tckesr. the user may change the external clock frequency or halt the external clock tcksre clock cycles afte r self-refresh entry is registered, howe ver, the clock must be restarted and stable tcksrx clock cycles before the device can exit self-r efresh operation. to protect dram internal delay on cke line to block the input signals, one nop (or desl) command is needed after self-refresh entry. the procedure for exiting self-refresh requ ires a sequence of events. first, t he clock must be stable tcksrx prior to cke going back high. once a self-refresh exit command (srex, combination of cke going high and either nop or desl on command bus) is registered, a delay of at least txs must be satisfied before a valid command not requiring a locked dll can be issued to the device to allow for any internal refresh in progress. before a command which requires a locked dll can be applied, a delay of at least txsdll and applicable zqcal function requirements (tbd) must be satisfied. cke must remain high for the entire se lf-refresh exit period txsdll for proper operation except for self-refresh reentry. upon exit from self-refresh, the ddr3 sdram can be put back into se lf-refresh mode after waiting at least txs period and issuing one refresh command (refresh period of trfc). nop or desl commands must be registered on each positive clock edge during the self-refresh exit in terval txs. odt must be turned off during txsdll. the use of self-refresh mode introduces the possibility th at an internally timed refresh event can be missed when cke is raised for exit from self-refresh mode. upon exit from self-refresh, the ddr3 sdram requires a minimum of one extra refresh command before it is put back into self-refresh mode. tcksre tckesr txs odtloff + 0.5 x tck trp * 2 * 2 * 3 * 3 notes: 1. only nop or desl commands. 2. valid commands not requiring a locked dll. 3. valid commands requiring a locked dll. 4. one nop or desl commands. ck, /ck odt command self nop pall srex valid * 1 * 4 ta tb tc tc+1tc+2 te td tf tf+1 tf+2 tg+1 tg th+1 th cke tcksrx txsdll valid valid valid self-refresh entry and exit timing
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 122 power-down mode power-down is synchronously entered when cke is regist ered low (along with nop or desl command). cke is not allowed to go low while mode register set command, mp r operations, zqcal operations, dll locking or read/write operation are in progress. cke is allowed to go low while an y of other operations such as row activation, precharge or auto precharge and refresh are in progress, but power-down idd spec will not be applied until finishing those operations. the dll should be in a locked state when power-down is enter ed for fastest power-down exit timing. if the dll is not locked during power-down entry, the dll must be reset after exiting power-down mode for proper read operation and synchronous odt operation. dram design provides a ll ac and dc timing and voltage specification as well proper dll operation with any cke intensive operat ions as long as dram controller complies with dram specifications. during power-down, if all banks are closed after any in-progress commands are completed, the device will be in precharge power-down mode; if any bank is open after in -progress commands are completed, the device will be in active power-down mode. entering power-down deactivates the input and output buffers, excluding ck, /ck, odt, cke and /reset. to protect dram internal delay on cke line to block the input signals, multiple nop or desl commands are needed during the cke switch off and cycle(s) after this timing period are defined as tcpded. cke_low will result in deactivation of command and address receivers after tcpded has expired. [power-down entry definitions] status of dram mr0 bit a12 dll pd exit relevant parameters active (a bank or more open) don?t care on fast txp to any valid command precharged (all banks precharged) 0 off slow txp to any valid command. since it is in precharge state, commands here will be act, ar, mrs, pre or pall . txpdll to commands who need dll to operate, such as read, reada or odt control line. precharged (all banks precharged) 1 on fast txp to any valid command also the dll is disabled upon entering precharge power-do wn for slow exit mode, but the dll is kept enabled during precharge power-down for fast exit mode or active power-down. in power-down mode, cke low, reset high and a stable clock signal must be maintained at the input s of the ddr3 sdram, and odt should be in a valid state but all other input signals are ?don?t care? (if reset goe s low during power-down, the dram will be out of pd mode and into reset state). cke low must be maintain ed until tpd has been satisfied. power-down duration is limited by 9 times trefi of the device. the power-down state is synchronously exited when cke is registered high (along with a nop or desl command). cke high must be maintained until tcke has been satisfied. a valid, executable command can be applied with power-down exit latency, txp and/or txpdll after cke goes high. power-down exit latency is defined at ac characteristics table of this data sheet.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 123 timing diagrams for proposed cke with power-down entry, power-down exit ck command cke dq(bl8) /ck t5 t7 t8 t9 t10 t11 t0 t1 t6 t12 tx tx+1 out 0 out 1 out 2 out 3 vih read ba valid nop dq(bc4) out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 trdpden tcpded tpd tis rl = cl + al = 5 (al = 0) nop power-down entry after read and read with auto precharge t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 tn ck ba command cke /ck t10 t14 t15 t16 t17 t18 writa valid nop nop nop tcpded tpd twr * note: twr is programmed through mrs. wl=5 twrapden tis start internal precharge in 0 in 1 in 2 in 3 in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 dq(bc4) dq(bl8) power-down entry after write with auto precharge
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 124 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 ck ba command cke /ck t10 tx tx+1 tx+2 tx+3 write valid nop nop tcpded tpd twr wl=5 twrpden tis in 0 in 1 in 2 in 3 in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 dq(bl8) dq(bc4) power-down entry after write t0 t1 tn tn+1 tx ty txp tcpded tcke (min.) tpd ck command cke /ck enter power-down mode note: valid command at t0 is act, nop, desl or precharge with still one bank remaining open after completion of precharge command. exit power-down tih tih tis tis valid nop nop nop nop nop nop nop valid nop nop nop nop n active power-down entry and exit timing diagram t0 t1 tn tn+1 tx ty txp tcpded tcke (min.) tpd ck command cke /ck enter power-down mode exit power-down tih tih tis tis nop nop nop nop nop nop nop valid nop nop nop1 nop n precharge power-down (fast exit mode) entry and exit
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 125 t0 t1 tn tx ty ck command cke /ck tn+1 enter power-down mode exit power-down nop nop nop nop nop nop nop nop nop valid nop valid nop no txp txpdll tcpded tcke (min.) tpd tih tih tis tis precharge power-down (slow exit mode) entry and exit t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck command cke /ck nop nop ref tcpded trefpden tis refresh command to power-down entry t0 t1 t2 t3 t4 tn end ck command cke /ck tn+1 tn+2 nop nop act tcpded tactpden tpd tis active command to power-down entry
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 126 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 end ck command cke /ck nop nop pre/ pall tcpded tprepden tis precharge/precharge all command to power-down entry t0 t1 t2 t3 tn tn+1 tn+2 tn+3 tn+4 tn+5 tn+6 tn+7 ck command cke /ck mrs nop nop nop nop nop tmrspden tcpded tis mrs command to power-down entry
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 127 timing values txxxpden parameters status of dram last command before cke_low parameter parameter value unit idle or active activate tactpden 1 nck idle or active precharge tprpden 1 nck active read/reada trdpden rl + 4 + 1 nck active writ for bl8mrs, bl8otf, bc4o tf twrpden wl + 4 + (twr/tck (avg)) * 1 nck active writ for bc4mrs twrpden wl + 2 + (twr/tck (avg))* 1 nck active writa for bl8mrs, bl8otf, bc4otf twrapden wl + 4 + wr* 2 + 1 nck active writa for bc4mrs twrapden wl + 2 + wr* 2 + 1 nck idle refresh trefpden 1 nck idle mode register set tmrspden tmod notes: 1. twr is defined in ns, for calculation of twrpden, it is necessary to round up twr / tck to next integer. 2. wr in clock cycles as programmed in mode register. power-down entry and exit clarification case 1: when cke registered low for power-down entry, tpd must be satisfied before cke can be registered high for power- down exit. case 1a: after power-down exit, tcke must be satisfied before cke can be registered low again. t0 t1 tn tn+1 tx ty tcpded tcke tpd ck command cke /ck enter power-down exit power-down tih tih tis tis nop nop nop nop nop nop nop nop nop nop nop nop nop n power-down entry/exit clarifications (1)
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 128 case 2: for certain cke intensive operations, for example, repeated "pd exit - refresh - pd entry" sequence, the number of clock cycles between pd exit and pd entry may be insuffi cient to keep the dll updated . therefore the following conditions must be met in addition to tpd in order to maintain proper dram operation when refresh commands is issued in between pd exit and pd entry. power-down mode can be used in conjunction with refresh command if the following conditions are met: 1. txp must be satisfied before issuing the command 2. txpdll must be satisfied (referenced to registra tion of pd exit) before next power-down can be entered. t0 t1 tn tn+1 tx ty tcpded tcke (min.) txpdll (min.) tpd ck command cke /ck enter power-down exit power-down tih tih tis tis txp nop nop nop nop nop nop nop nop nop nop nop ref nop power-down entry/exit clarifications (2) case 3: if an early pd entry is issued after refresh command, once pd exit is issued, nop or desl with cke high must be issued until trfc from the refresh command is satisfied. this means cke cannot be de-asserted twice within trfc window. t0 t1 tn tn+1 tx ty tcpded tcke (min.) trfc (min.) tpd txpdll ck command cke /ck enter power-down note: * synchronous odt timing starts at the end of txpdll (min.) exit power-down tih tih tis tis ref nop nop nop nop nop nop nop nop nop nop nop valid n power-down entry/exit clarifications (3)
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 129 input clock frequency change during precharge power-down once the ddr3 sdram is initialized, the ddr3 sdram requires the clock to be ?s table? during almost all states of normal operation. this means once t he clock frequency has been set and is to be in the ?stable state?, the clock period is not allowed to deviate except for what is allowed for by the clock jitter and ssc (spread spectrum clocking) specifications. the input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1) self-refresh mode and (2) precharge power-down mode. outside of these two modes, it is illegal to change the clock frequency. for the first condition, once the ddr3 sdram has been successfully placed in to self- refresh mode and tcksre has been satisfied, the state of the clock becomes a don?t care. once a don?t care, changing the clock frequency is permissible, provided t he new clock frequency is stable prior to tcksrx. when entering and exiting self-refresh mode fo r the sole purpose of changing the clo ck frequency, the self-refresh entry and exit specifications must still be met as outlined in self-refresh section. the second condition is when the ddr3 sdram is in prechar ge power-down mode (either fast exit mode or slow exit mode.) odt must be at a logic low ensuring rtt is in an off state prior to entering precharge power-down mode and cke must be at a logic low. a minimum of tcksre mu st occur after cke goes low before the clock frequency may change. the ddr3 sdram input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed gra de. during the input clock frequency change, odt and cke must be held at stable low levels. once the inpu t clock frequency is changed, stable new clocks must be provided to the dram tcksrx before precharge power-down may be exited; after precharge power-down is exited and txp has expired, the dll must be reset via mrs. depending on the new clock frequency additional mrs commands may need to be issued to appropriately set the wr, cl, and cwl with cke continuously registered high. during dll relock period, odt must rema in low. after the dll lock time, the dram is ready to operate with new clock frequency. this process is depicted in the fi gure clock frequency change in precharge power-down mode. ck cke t2 tb tc tc+1 td t0 t1 ta /ck td+1 enter precharge power-down mode odt command te te+1 dqs, /dqs nop nop nop nop nop mrs valid exit precharge power-down mode txp high-z high-z frequency change nop address valid tih tis tcksre new clock frequency previous clock frequency tcpded tcksrx dll reset taofpd/taof dq dm tdllk notes: 1. applicable for both slow exit and fast exit precharge power-down. 2. tcksre and tcksrx are self-refresh mode specifications but the values they represent are applicable here. 3. taofpd and taof must be satisfied and outputs high-z prior to t1; refer to odt timing for exact requirements. clock frequency change in precharge power-down mode
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 130 on-die termination (odt) odt (on-die termination) is a featur e of the ddr3 sdram that allows the dram to turn on/off termination resistance for each dq, dqs, /dqs and dm for 8 configuration (and tdqs, /tdqs for 8 configuration, when enabled via a11=1 in mr1) via the odt control pin. for 16 configuration odt is appl ied to each dqu, dql, dqsu, /dqsu, dqsl, /dqsl, dmu and dml signal via the odt control pin. the od t feature is designed to improve signal integrity of the memory channel by allo wing the dram controller to independently turn on/off termination resistance for any or all dram devices. the odt feature is turned off and not supported in self-refresh mode. a simple functional representation of the dram odt feature is shown in fi gure functional representation of odt. to other circuitry like rcv, ... odt vddq/2 rtt switch dq, dqs, dm, tdqs functional representation of odt the switch is enabled by the internal odt control logi c, which uses the external odt pin and other control information, see below. the value of rtt is dete rmined by the settings of mode register bits (see mr1 programming figure in the section progr amming the mode register). the odt pin will be ignored if the mode register mr1 is programmed to disable odt and in self-refresh mode. odt mode register and odt truth table the odt mode is enabled if either of mr1 bits a2 or a6 or a9 are non-zero. in this case the value of rtt is determined by the settings of those bits. application: controller sends writ command together with odt asserted. ? one possible application: t he rank that is being writt en to provide termination. ? dram turns on termination if it sees odt asserted (except odt is disabled by mr) ? dram does not use any write or read command decode information ? the termination truth table is show n in the termination truth table [termination truth table] odt pin dram termination state 0 off 1 on, (off, if disabled by mr1 bits a2, a6 and a9 in general)
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 131 synchronous odt mode synchronous odt mode is selected whenever the dll is turned on and locked. based on the power-down definition, these modes are: ? active mode ? idle mode with cke high ? active power-down mode (regardless of mr0 bit a12) ? precharge power-down mode if dll is enabled during precharge power-down by mr0 bit a12. in synchronous odt mode, rtt will be turned on or off odt lon clock cycles after odt is sampled high by a rising clock edge and turned off odtloff clock cy cles after odt is registered low by a rising clock edge. the odt latency is tied to the write latency (wl) by: odtlon = wl ? 2; odtloff = wl ? 2. odt latency and posted odt in synchronous odt mode, the additive latency (al) prog rammed into the mode register (mr1) also applies to the odt signal. the dram internal odt signal is delayed for a number of clock cycles defined by the additive latency (al) relative to the external odt signal. odtlon = cwl + al ? 2; odtloff = cwl + al ? 2. for details, refer to ddr3 sdram latency definitions. [odt latency table] parameter symbol value unit odt turn-on latency odtlon wl ? 2 = cwl + al ? 2 nck odt turn-off latency odtloff wl ? 2 = cwl + al ? 2 nck synchronous odt timing parameters in synchronous odt mode, the following timing parameters apply (see synchronous odt timing examples (1)): odtllow, odtlloff, taon,(min.), (max.), taof,(min.),(max.) minimum rtt turn-on time (t aon min) is the point in time when the device leaves high impedance and odt resistance begins to turn on. maximum rtt turn-on time (taon max) is the point in time when the odt resi stance is fully on. both are measured from odtlon. minimum rtt turn-off time (tao f min ) is the point in time when the device starts to turn-off the odt resistance. maximum rtt turn-off time (t aof max) is the point in time when the on-die termination has reached high impedance. both are measured from odtloff. when odt is asserted, it must remain high until odth4 is satisfied. if a write command is registered by the sdram with odt high, then odt must remain high unti l odth4 (bl4) or odth8 (bl8) after the write command (see figure synchronous odt timing examples (2)). od th4 and odth8 are measured from odt registered high to odt registered low or from the registration of a write command until odt is registered low.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 132 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 end ck cke intodt odt rtt /ck odth4 (min.) al = 3 al = 3 odtlon = cwl + al ? 2 odtloff = cwl + al ? 2 cwl ? 2 rtt taof (max.) taof (min.) taon (max.) taon (min.) synchronous odt timing examples (1): al=3, cwl = 5; odtlon = al + cwl - 2 = 6; odtloff = al + cwl - 2 = 6 ck cke command odt dram_rtt /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 odth4 odth4 odth4 odtlon = wl ? 2 odtlon = wl ? 2 odtloff = wl ? 2 odtloff = wl ? 2 wrs4 rtt rtt taon (max.) taon (min.) taof (max.) taof (min.) taof (max.) taof (min.) taon (min.) taon (max.) synchronous odt timing examples (2)*: bc4, wl = 7 odt must be held high for at least odth4 after assertion (t1); odt must be kept high odth4 (bc4) or odth8 (bl8) after write command (t7). odth is measured from od t first registered high to odt first registered low, or from registration of write command with odt high to odt r egistered low. note that although odth4 is satisfied from odt registered high at t6 odt must not go low be fore t11 as odth4 must also be satisfied from the registration of the write command at t7.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 133 odt during reads as the ddr3 sdram cannot terminate and drive at the same time, rtt must be disabled at least half a clock cycle before the read preamble by driving the odt pin low appropriately. rtt may nominally not be enabled until one clock cycle after the end of the post-amble as shown in the example in the figure below. note that odt may be disabled earlier before the read and enabled later after the read than shown in this example in the figure below. odt must be disabled externally during reads by driving odt low. (example: cl = 6; al = cl - 1 = 5; rl = al + cl = 11; cwl = 5; odtlon = cwl + al -2 = 8; odtloff = cwl + al - 2 = 8) dram_rtt ck command address odt dqs, /dqs dq /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 end rl = al + cl odtloff = wl ? 2 = cwl + al ? 2 odtlon = wl ? 2 = cwl + al ? 2 read a out 0 rtt rtt out 1 out 2 out 3 out 4 out 5 out 6 out 7 taon (min.) taon (max.) taof (max.) taof (min.) example of odt during reads
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 134 dynamic odt in certain application cases and to further enhance signal int egrity on the data bus, it is desirable that the termination strength of the ddr3 sdram c an be changed without issuing an mrs command. this requirement is supported by the ?dynamic odt? feature as described as follows: functional description: the dynamic odt mode is enabled if bit a9 or a10 of mr2 is set to ?1?. the function and is described as follows: ? two rtt values are available: rtt_nom and rtt_wr. ? the value for rtt_nom is pre-sele cted via bits a[9,6,2] in mr1 ? the value for rtt_wr is pre-selected via bits a[10,9] in mr2 ? during operation without write commands, the termination is controlled as follows: ? nominal termination strength rtt_nom is selected. ? termination on/off timing is controlled vi a odt pin and latencies odtlon and odtloff. ? when a write command (writ, writa, wrs4, wrs8, wr as4, wras8) is registered, and if dynamic odt is enabled, the termination is controlled as follows: ? a latency odtlcnw after the write command, termination strength rtt_wr is selected. ? a latency odtlcwn8 (for bl8, fixed by mrs or selected otf) or odtlcwn4 (for bc4, fixed by mrs or selected otf) after the write command, termination strength rtt_nom is selected. ? termination on/off timing is controll ed via odt pin and odtlon, odtloff. table latencies and timing parameters relevant for dynami c odt shows latencies and timing parameters, which are relevant for the on-die terminat ion control in dynamic odt mode: when odt is asserted, it must remain high until odth4 is satisfied. if a write command is registered by the sdram with odt high, then odt must remain high until odth4 (bc4) or odth8 (bl8) after the write command (see the figure synchronous odt timing examples (2)). odth 4 and odth8 are measured from odt registered high to odt registered low or from the registration of a write command until odt is registered low. [latencies and timing parameters relevant for dynamic odt] parameters symbols defined from defined to definition for all ddr3 speed bins unit odt turn-on latency odtlon registering external odt signal high turning termination on odtlon = wl ? 2.0 nck odt turn-off latency odtloff registering external odt signal low turning termination off odtloff = wl ? 2.0 nck odt latency for changing from rtt_nom to rtt_wr odtlcnw registering external write command change rtt strength from rtt_nom to rtt_wr odtlcnw = wl ? 2.0 nck odt latency for change from rtt_wr to rtt_nom (bc4) odtlcwn4 registering external write command change rtt strength from rtt_wr to rtt_nom odtlcwn4 = 4 + odtloff nck odt latency for change from rtt_wr to rtt_nom (bl8) odtlcwn8 registering external write command change rtt strength from rtt_wr to rtt_nom odtlcwn8 = 6 + odtloff nck minimum odt high time after odt assertion odth4 registering odt high odt registered low odth4 (min.) = 4 nck minimum odt high time after write (bc4) odth4 registering write with odt high odt registered low odth4 (min.) = 4 nck minimum odt high time after write (bl8) odth8 registering write with odt high odt registered low odth8 (min.) = 6 nck rtt change skew tadc odtlcnw odtlcwn rtt valid 0.3ns to 0.7ns tck (avg)
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 135 mode register settings for dynamic odt mode: the table mode register for rtt selection shows the mode register bits to select rtt_nom and rtt_wr values. [mode register for rtt selection] mr1 mr2 a9 a6 a2 rtt_nom (rzq) rtt_nom ( ? ) a10 a9 rtt_wr (rzq) rtt_wr* 1 ( ? ) 0 0 0 off off 0 0 dynamic odt off: write does not affect rtt value 0 0 1 rzq/4 60 0 1 rzq/4 60 0 1 0 rzq/2 120 1 0 rzq/2 120 0 1 1 rzq/6 40 1 1 reserved reserved 1 0 0 rzq/12* 2 20 ? ? ? ? 1 0 1 rzq/8* 2 30 ? ? ? ? 1 1 0 reserved reserved ? ? ? ? 1 1 1 reserved reserved ? ? ? ? notes: 1. rzq = 240 ? . 2. if rtt_nom is used during writes, only the values rzq/2, rzq/4 and rzq/6 are allowed. odt timing diagrams ck command odt rtt dqs, /dqs dq /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 in 0 wrs4 odtlcnw odtlcwn4 odtlon odtloff odth4 odth4 wl rtt_nom rtt_nom rtt_wr taon (min.) tadc (min.) tadc (min.) taof (min.) tadc (max.) tadc (max.) taon (max.) taof (max.) in 1 in 2 in 3 dynamic odt: behavior with odt being asserted before and after the write* note: example for bc4 (via mrs or otf), al = 0, cwl = 5. odth4 applies to first registering odt high and to the registration of the write command. in this example odth4 would be satisfied if odt is low at t8 (4 clocks after the write command).
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 136 ck command odt rtt dqs, /dqs dq /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 odth4 rtt_nom taon (min.) taon (max.) taof (min.) taof (max.) odtlon odtloff dynamic odt*: behavior without write command; al = 0, cwl = 5 note: odth4 is defined from odt registered high to odt r egistered low, so in this example odth4 is satisfied; odt registered low at t5 would also be legal. ck command odt rtt dqs, /dqs dq /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 rtt_wr taon (min.) tadc (max.) taof (min.) taof (max.) odtlcnw odtlcwn8 odtlon odtloff wrs8 in 0 wl odth8 in 1 in 2 in 3 in 4 in 5 in 6 in 7 dynamic odt*: behavior with odt pin being asserted together with write command for duration of 6 clock cycles note: example for bl8 (via mrs or otf), al = 0, cwl = 5. in this example odth8 = 6 is exactly satisfied.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 137 ck command odt rtt dqs, /dqs dq /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 rtt_wr rtt_nom taon (min.) tadc (max.) taof (min.) taof (max.) tadc (min.) tadc (max.) odtlcnw odtlcwn4 odtlon odtloff wrs4 in 0 wl odth4 in 1 in 2 in 3 dynamic odt*: behavior with odt pin being asserted together with write command for a duration of 6 clock cycles, example fo r bc4 (via mrs or otf), al = 0, cwl = 5. note: odth4 is defined from odt registered high to odt r egistered low, so in this example odth4 is satisfied; odt registered low at t5 would also be legal. ck command odt rtt dqs, /dqs dq /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 odtlcnw odtlcwn4 odtlon odtloff wrs4 in 0 wl tadc (max.) taof (max.) rtt_wr taon (min.) taof (min.) odth4 in 1 in 2 in 3 dynamic odt*: behavior with odt pin being asserted together with write command for duration of 4 clock cycles note: example for bc4 (via mrs or otf), al = 0, cwl = 5. in this example odth4 = 4 is exactly satisfied.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 138 asynchronous odt mode asynchronous odt mode is selected when dram runs in dll-on mode, but dll is temporarily disabled (i.e. frozen) in precharge power-down (by mr0 bit a12). precharge power-down mode if dll is disabled during precharge power-down by mr0 bit a12. in asynchronous odt timing mode, internal odt command is not delayed by additive latency (al) relative to the external odt command. in asynchronous odt mode, the following timing param eters apply (see figure asynchronous odt timings): taonpd (min.), (max.), taofpd (min.),(max.) minimum rtt turn-on time (taonpd (min.)) is the point in time when the device termination circuit leaves high impedance state and odt resistance begins to turn on. maxi mum rtt turn-on time (taonpd (max.)) is the point in time when the odt resistance is fully on. taonpd (min.) and taonpd (max.) are measured from odt being sampled high. minimum rtt turn-off time (taofpd (min.)) is the point in time when the devices termination circuit starts to turn off the odt resistance. maximum odt turn-o ff time (taofpd (max.)) is the point in time when the on-die termination has reached high impedance. taofpd (min.) and taofpd (max.) are measured from odt being sampled low. ck odt cke dram_rtt /ck rtt tih tis tih tis taonpd (max.) taonpd (min.) taofpd (max.) taofpd (min.) asynchronous odt timings on ddr3 sdram with fast odt tr ansition: al is ignored in precharge power-down, odt receiver remains active, however no read or write command can be issued, as the respective address/command receivers may be disabled. [asynchronous odt timing parameters for all speed bins] symbol parameters min. max. unit taonpd asynchronous rtt turn-on delay (power-down with dll frozen) 2 8.5 ns taofpd asynchronous rtt turn-off delay (power-down with dll frozen) 2 8.5 ns [odt for power-down (with dll frozen) entry and exit transition period] description min. max. odt to rtt turn-on delay min {odtlon tck + taon(min.); taonpd(min.) } max {odtlon tck + taon(max.); taonpd(max.) } min { (wl ? 2.0) tck + taon(min.); taonpd(min.) } max {(wl ? 2.0) tck + taon(max.); taonpd(max.) } odt to rtt turn-off delay min { odtloff tck +taof(min.); taofpd(min.) } max { odtloff tck + taof(max.); taofpd(max.) } min { (wl ? 2.0) tck +taof(min.); taofpd(min.) } max {(wl ? 2.0) tck + taof(max.); taofpd(max.) } tanpd wl ? 1.0
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 139 synchronous to asynchronous odt mode transition during power-down entry if dll is selected to be frozen in precharge power-down mode by the setting of bit a12 in mr0 to 0 there is a transition period around power-down entry, where the ddr3 sdram may show either synchronous or asynchronous odt behavior. this transition period ends when cke is first registered low and starts tanpd before that. if there is a refresh command in progress while cke goes low, then the transiti on period ends trfc after the refresh command. tanpd is equal to (wl ? 1.0) and is counted (backwards) from the clo ck cycle where cke is first registered low. odt assertion during the transition period may result in an rtt change as early as the smaller of taonpd(min.) and (odtlon tck + taon(min.)) and as late as t he larger of taonpd(max.) and (odtlon tck + taon(max.)). odt de-assertion during the transition per iod may result in an rtt change as ear ly as the smaller of taofpd(min.) and (odtloff tck + taof(min.)) and as late as t he larger of taofpd(max.) and (odtloff tck + taof(max.)). note that, if al has a large value, the range where rtt is uncertain becomes quite large. the figure below shows the three different cases: odt_a, synchronous behavior before tanpd; odt_b has a state change during the transition period; odt_c show s a state change after the transition period. ck odt command cke dram_rtt_a_sync odt_a_sync odt_b_tran dram_rtt_b_tran dram_rtt_c_async odt_c_async /ck taof (min.) taof (max.) pd entry transition period tanpd trfc odtloff ref nop nop rtt rtt odtloff + taofpd (min.) taofpd (max.) taofpd (max.) taofpd (min.) taofpd (min.) odtloff + taofpd (max.) synchronous to asynchronous transition during precharge power-down (with dll frozen) entry (al = 0; cwl = 5; tanpd = wl ? 1 = 4)
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 140 asynchronous to synchronous odt mode transition during power-down exit if dll is selected to be frozen in precharge power-down mode by the setting of bit a12 in mr0 to 0, there is also a transition period around power-down exit, where either sy nchronous or asynchronous response to a change in odt must be expected from the ddr3 sdram. this transition period starts tanpd before cke is first registered high, a nd ends txpdll after cke is first registered high. tanpd is equal to (wl ? 1.0) and is counted backward from the cloc k cycle where cke is first registered high. odt assertion during the transition period may result in an rtt change as early as the smaller of taonpd(min.) and (odtlon tck + taon(min.)) and as late as the larger of taonpd(max.) and (odtlon tck + taon(max.)). odt de-assertion during the transition per iod may result in an rtt change as ear ly as the smaller of taofpd(min.) and (odtloff tck + taof(min.)) and as late as the larger of taofpd(max.) and (odtloff tck + taof(max.)). see odt for power-down (with dll frozen) entry and exit transition period table. note that, if al has a large value, the range where rtt is uncertain become s quite large. the figure below shows the three different cases: odt_c, asynchronous respons e before tanpd; odt_b has a state change of odt during the transition period; odt_a shows a st ate change of odt after the transition period with synchronous response. rtt rtt t1 t3 t5 t7 t9 t11 t13 t15 t17 t19 t21 t23 t25 t27 t29 t31 t33 t35 ck command cke dram_rtt_a_sync odt_a_sync odt_b_tran dram_rtt_b_tran dram_rtt_c_async odt_c_async /ck pd exit transition period tanpd txpdll taof (min.) taof (max.) odtloff taofpd (max.) taofpd (min.) odtloff + taof (max.) odtloff + taof (min.) taofpd (max.) taofpd (min.) nop nop asynchronous to synchronous transition during pr echarge power-down (with dll frozen) exit (cl = 6; al = cl - 1; cwl = 5; tanpd= wl ? 1 = 9)
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 141 asynchronous to synchronous odt mode during short cke high and short cke low periods if the total time in precharge power-down state or idle stat e is very short, the transition periods for power-down entry and power-down exit may overlap. in this case the resp onse of the ddr3 sdram rtt to a change in odt state at the input may be synchronous or asynchronous from the st art of the power-down entry transition period to the end of the pd exit transition perio d (even if the entry period ends later than the exit period). if the total time in idle state is ve ry short, the transition periods for power-down exit and power-down entry may overlap. in this case the respons e of the ddr3 sdram rtt to a change in odt state at the input may be synchronous or asynchronous from the start of the power-down exit transiti on period to the end of the power-down entry transition period. note that in the bottom part of figure below it is assum ed that there was no refresh command in progress when idle state was entered. ref nop nop nop nop ck command cke cke /ck tanpd trfc pd entry transition period pd exit transition period tanpd txpdll tanpd txpdll tanpd short cke high transition period short cke low transition period txpdll transition period for short cke cycles with entry and exit period overlapping (al = 0, wl = 5, tanpd = wl ? 1 = 4)
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 142 zq calibration zq calibration command is used to calibrate dram ron and odt values. ddr3 sdram needs longer time to calibrate ron and odt at initialization and relatively smaller time to perform periodic calibrations. zqcl command is used to perform the initial calibratio n during power-up initialization sequence. this command may be issued at any time by the controller depending on the system environment. zqcl command triggers the calibration engine inside the dram and once calibration is achieved the calibrated val ues are transferred from calibration engine to dram i/o which gets re flected as updated ron and odt values. the first zqcl command issued after reset is allowed a timing period of tzqinit to perform the full calibration and the transfer of values. all other zqcl commands except th e first zqcl command issued after reset is allowed a timing period of tzqoper. zqcs command is used to perform periodic calibrations to account for voltage and temperature variations. a shorter timing window is provided to perform the calibration and tran sfer of values as defined by timing parameter tzqcs. one zqcs command can effectively correct a minimum of 0.5% (zqcorrection) of ron and rtt impedance error within 64nck for all speed bins assuming the maximum sens itivities specified in the ?output driver voltage and temperature sensitivity? an d ?odt voltage and temperature sensitivity? tables. the a ppropriate interval between zqcs commands can be determined from these tables and other application-specific parameters. one method for calculating the interval between zqcs commands, given the te mperature (tdriftrate) and voltage (vdriftrate) drift rates that the sdram is subject to in the application, is illustrated. the interval could be defined by the following formula:

where tsens = max(drttdt, drondtm) and vsens = ma x(drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5%/ c, vsens = 0.15%/mv, tdriftrate = 1 c/sec and vdriftrate = 15mv/sec, then the interval between zqcs commands is calculated as:
no other activities should be performed on the dram channel by the controller for the durat ion of tzqinit, tzqoper or tzqcs. the quiet time on the dram channel allows in accurate calibration of ron and odt. once dram calibration is achieved the dram should disabl e zq current consumption path to reduce power. all banks must be precharged and trp met before zqcl or zqcs commands are issued by the controller. zq calibration commands can also be issued in parallel to dll lock time when coming out of self-refresh. upon self- refresh exit, ddr3 sdram will not perform an io calibration without an explicit zq calibration command. the earliest possible time for zq calibration command (s hort or long) after self-refresh exit is txs. in dual rank systems that s hare the zq resistor between devices, the controller must not allow any overlap of tzqoper or tzqinit or tzqcs between ranks. ck a10 address cke dq bus* 2 notes: 1. odt must be disabled via odt signal or mrs during calibration procedure. 2. all device connected to dq bus should be high impedance during calibration. command nop/desl nop/desl zqcs valid valid zqcl hi-z activities hi-z activities a10 = l a10 = h x x tzqinit or tzq oper tzqcs zq calibration
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 143 zq external resistor value and tolerance ddr3 sdram has a 240 ? , 1% tolerance external resistor connecting from the ddr3 sdram zq pin to ground. the resister can be used as single dram per resistor.
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 144 package drawing 78-ball fbga solder ball: lead free (sn-ag-cu) 8.6 0.1 13.0 0.1 0.1 s 0.2 s 1.20 max. 0.35 0.05 s b a 0.8 9.6 1.6 6.4 unit: mm 0.2 s b 78- 0.45 0.05 0.15 m sa b eca-ts2-0242-01 0.2 s a 0.8 index mark index mark
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 145 96-ball fbga solder ball: lead free (sn-ag-cu) 8.6 0.1 index mark 13.5 0.1 0.1 s 0.2 s 1.20 max. 0.35 0.05 s b a 0.8 12.0 1.6 6.4 unit: mm 0.2 s b 96- 0.45 0.05 0.15 m sa b eca-ts2-0243-01 0.2 s a 0.8 0.4 index mark
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 146 recommended soldering conditions please consult with our sales offices for solder ing conditions of the edj1108babg, edj1116babg. type of surface mount device edj1108babg: 78-ball fbga < lead free (sn-ag-cu) > edj1116babg: 96-ball fbga < lead free (sn-ag-cu) >
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 147 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
eol produ ct edj1108babg, edj1116babg data sheet e1248e40 (ver. 4.0) 148 m01e0706 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] be aware that this product is for use in typical electronic equipment for general-purpose applications. elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] usage in environments with special characteristics as listed below was not considered in the design. accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. example: 1) usage in liquids, including water, oils, chemicals and organic solvents. 2) usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) usage involving exposure to significant amounts of corrosive gas, including sea air, cl 2 , h 2 s, nh 3 , so 2 , and no x . 4) usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) usage in places where dew forms. 6) usage in environments with mechanical vibration, impact, or stress. 7) usage near heating elements, igniters, or flammable items. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

▲Up To Search▲

Price & Availability of EDJ1108BABG-DG-E

	To Download EDJ1108BABG-DG-E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .